Multi-tiered hierarchical high speed switch matrix structure for very high-density complex programmable logic devices

• US 5,818,254 A
• Filed: 06/02/1995
• Issued: 10/06/1998
• Est. Priority Date: 06/02/1995
• Status: Expired due to Term

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Agrawal, Om P., Sharpe-Geisler, Bradley A.
• Primary Examiner(s): Tokar, Michael J.
• Assistant Examiner(s): ROSEEN, RICHARD R
• Application Number:
  US08/459,230
• Time in Patent Office: 1,222 Days
• Field of Search: 326/38, 326/39, 326/41
• US Class Current: 326/39
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17736 Structural details of routing resources

Abstract

A hierarchical switch matrix in a very high-density programmable logic device (CPLD) interconnects a multiplicity of programmable logic blocks in the CPLD. A new level of functionality coupled with high speed is provided by the hierarchical switch matrix. The hierarchical switch matrix includes three levels, a global switch matrix, a segment switch matrix and a block switch matrix. The block switch matrix provides a high speed signal path for signals within a programmable logic block. The segment switch matrix provides a high speed means of communication for signals within a segment, while the global switch matrix provides a high speed path for communication between segments. The hierarchical switch matrix of this invention provides a fixed, path independent, uniform, predictable and deterministic time delay for each group of signals routed through the hierarchical switch matrix.

Claims

1. In an integrated circuit having a plurality of programmable logic circuits wherein each programmable logic circuit includes a plurality of input lines and a plurality of output lines, a programmable hierarchical switch matrix comprising:

(i) a first programmable switch matrix having a multiplicity of output lines and a multiplicity of input lines;

wherein said first programmable switch matrix selectively connects and disconnects each line in said multiplicity of said programmable first switch matrix input lines to and from at least one line in said multiplicity of first programmable switch matrix output lines;

said first programmable switch matrix output lines are connected to a plurality of input lines of one of said plurality of programmable logic circuits;

and a signal path through said first programmable switch matrix and said one of said plurality of programmable logic circuits defines a first level of said hierarchical switch matrix;

(ii) a second programmable switch matrix having;

a multiplicity of programmable demultiplexers wherein each programmable demultiplexer has an input terminal and N output terminals, where N is an integer, and each programmable demultiplexer selectively connects said input terminal to one of said N output terminals and disconnects remaining output terminals of said N output terminals from said input terminal;

a multiplicity of input lines wherein each input line is connected to one input terminal of one demultiplexer in said plurality of demultiplexers; and

a multiplicity of output lines wherein each output line is connected to an output terminal of at least one demultiplexer in said plurality of demultiplexers;

wherein a set of output lines in said multiplicity of said second programmable switch matrix output lines is coupled to a set of input lines in said multiplicity of said programmable first switch matrix input lines so that another signal path through said second programmable switch matrix, said first programmable switch matrix, and said one of said plurality of programmable logic circuits defines another level of said hierarchical switch matrix; and

a set of output lines in a plurality of output lines of said one of said plurality of programmable logic circuits is coupled to a group of input lines in said multiplicity of input lines of said programmable second switch matrix so that a signal from said programmable logic circuit has a signal route to said second programmable switch matrix without passing through said first switch matrix.

2. The programmable hierarchical switch matrix as in claim 1 wherein said second programmable switch matrix is a programmable segment switch matrix.

3. The programmable hierarchical switch matrix as in claim 1 wherein said second programmable switch matrix is a programmable global switch matrix.

4. The programmable hierarchical switch matrix as in claim 1 wherein said set of said plurality of output lines of said one of said programmable logic circuits is connected to a first group of lines in said multiplicity of input lines of said first programmable switch matrix.

5. The programmable hierarchical switch matrix as in claim 4 wherein said set of said plurality of output lines of said one of said programmable logic circuits includes a plurality of macrocell feedback lines.

6. The programmable hierarchical switch matrix as in claim 4 wherein said set of said plurality of output lines of said one of said programmable logic circuits includes a plurality of I/O pin feedback lines.

7. The programmable hierarchical switch matrix as in claim 1 wherein said set of output lines in said plurality of output lines of said one of said programmable logic circuits includes a plurality of macrocell feedback lines.

8. The programmable hierarchical switch matrix as in claim 1 wherein said set of output lines in said plurality of output lines of said one of said programmable logic circuits includes a set of I/O pin feedback lines.

9. The programmable hierarchical switch matrix as in claim 1 wherein said multiplicity of programmable demultiplexers and said multiplicity of input lines of said second programmable switch matrix are arranged in a plurality of strips wherein each strip is associated with one of said plurality of programmable logic circuits.

10. The programmable hierarchical switch matrix as in claim 1 wherein said plurality of programmable logic circuits includes four programmable logic circuits.

11. The programmable hierarchical switch matrix as in claim 1 further comprising:

(iii) a third programmable switch matrix having a multiplicity of input lines and a multiplicity of output lines;

wherein said third programmable switch matrix selectively connects and disconnects each line in said multiplicity of said third programmable switch matrix input lines to and from at least one line in said multiplicity of said third programmable switch matrix output lines;

a set of output lines in said multiplicity of said third programmable switch matrix output lines is connected to a set of input lines in said multiplicity of said programmable second switch matrix input lines so that yet another signal path through said third programmable switch matrix, said second programmable switch matrix, said first programmable switch matrix, and said one of said plurality of programmable logic circuits defines yet another level of said hierarchical switch matrix.

12. The programmable hierarchical switch matrix as in claim 11 wherein said plurality of output lines of said one of said programmable logic circuits is connected to a first group of lines in said multiplicity of input lines of said first programmable switch matrix.

13. The hierarchical switch matrix of claim 11 wherein said multiplicity of output lines and said multiplicity of input lines of said third programmable switch matrix are a single multiplicity of bidirectional signal lines.

14. The programmable hierarchical switch matrix as in claim 11 wherein said multiplicity of output lines of said second programmable switch matrix is a group of input lines in said multiplicity of input lines of said third programmable switch matrix.

15. The programmable hierarchical switch matrix as in claim 11 wherein said multiplicity of programmable demultiplexers and said multiplicity of input lines of said second programmable switch matrix are arranged in a plurality of strips wherein each strip is associated with one of said plurality of programmable logic circuits.

16. The programmable hierarchical switch matrix as in claim 15 wherein said plurality of programmable logic circuits includes four programmable logic circuits.

17. In an integrated circuit having a plurality of programmable logic circuits wherein each programmable logic circuit includes a plurality of input lines and a plurality of output lines, a programmable hierarchical switch matrix comprising:

(i) a first programmable switch matrix having a multiplicity of output lines and a multiplicity of input lines;

wherein said first programmable switch matrix selectively connects and disconnects each line in said multiplicity of said programmable first switch matrix input lines to and from at least one line in said multiplicity of first programmable switch matrix output lines;

said first programmable switch matrix output lines are connected to a plurality of input lines of one of said plurality of programmable logic circuits; and

a signal path through said first programmable switch matrix and said one of said plurality of programmable logic circuits defines a first level of said hierarchical switch matrix;

(ii) a second programmable switch matrix having;

a multiplicity of programmable demultiplexers wherein each programmable demultiplexer has an input terminal and N output terminals, where N is an integer, and each programmable demultiplexer selectively connects said input terminal to one of said N output terminals and disconnects remaining output terminals of said N output terminals from said input terminal;

a multiplicity of input lines wherein each input line is connected to one input terminal of one demultiplexer in said plurality of demultiplexers; and

a multiplicity of bidirectional signal lines wherein each line in said multiplicity of bidirectional signal lines is coupled to an output terminal of one of said programmable demultiplexers;

wherein a set of bidirectional signal lines in said multiplicity of said second programmable switch matrix bidirectional signal lines is coupled to a set of input lines in said multiplicity of said programmable first switch matrix input lines so that another signal path through said second programmable switch matrix, said first programmable switch matrix, and said one of said plurality of programmable logic circuits defines another level of said hierarchical switch matrix; and

a set of output lines in a plurality of output lines of said one of said plurality of programmable logic circuits is coupled to a group of input lines in said multiplicity of input lines of said programmable second switch matrix so that a signal from said programmable logic circuit has a signal route to said second programmable switch matrix without passing through said first switch matrix.

18. The programmable hierarchical switch matrix as in claim 17 wherein said second programmable switch matrix is a programmable global switch matrix.

19. The programmable hierarchical switch matrix as in claim 17 wherein said set of output lines in said plurality of output lines of said one of said programmable logic circuits is connected to a first group of lines in said multiplicity of input lines of said first programmable switch matrix.

20. The programmable hierarchical switch matrix as in claim 19 wherein said set of output lines in said plurality of output lines of said one of said programmable logic circuits includes a plurality of macrocell feedback lines.

21. The programmable hierarchical switch matrix as in claim 19 wherein said set of output lines in said plurality of output lines of said one of said programmable logic circuits includes a plurality of I/O pin feedback lines.

22. In a very high density programmable logic device, a hierarchical switch matrix comprising:

(i) a programmable block switch matrix having a multiplicity of input lines and a multiplicity of output lines;

wherein said programmable block switch matrix selectively connects and disconnects each line in said multiplicity of programmable block switch matrix input lines to and from at least one line in said multiplicity of programmable block switch matrix output lines;

said programmable block switch matrix output lines are connected to a plurality of input lines of one of a plurality of programmable logic blocks; and

a first signal path through said first programmable switch matrix and said one of said plurality of programmable logic blocks defines a first level of said hierarchical switch matrix;

(ii) a programmable segment switch matrix having a multiplicity of input lines and a first bidirectional bus;

wherein said programmable segment switch matrix selectively connects and disconnects each line in said multiplicity of programmable segment switch matrix input lines to and from at least one line in said first bidirectional bus;

a set of lines in said plurality of output lines of said one of said plurality of programmable logic blocks is connected to a first group of lines in said multiplicity of input lines of said programmable segment switch matrix so that signals from said one of said plurality of programmable logic blocks are provided to said programmable segment switch matrix without passing through the programmable block switch matrix;

said multiplicity of programmable block switch matrix input lines is connected to said first bidirectional bus; and

a second signal path through said programmable segment switch matrix, said programmable block switch matrix, and said one of said plurality of programmable logic blocks defines a second level of said hierarchical switch matrix; and

(iii) a programmable global switch matrix having a multiplicity of bidirectional signal lines;

wherein said programmable global switch matrix selectively connects and disconnects each line in said multiplicity of programmable global switch matrix bidirectional signal lines to and from at least one line in said first bidirectional bus; and

a third signal path through said programmable global switch matrix, said programmable segment switch matrix, said programmable block switch matrix, and said one of said plurality of programmable logic blocks defines a third level of said hierarchical switch matrix.

23. The hierarchical switch matrix of claim 22 wherein said set of lines in said plurality of output lines of said one of said plurality of programmable logic blocks is connected to a first group of lines in said multiplicity of input lines of said programmable block switch matrix.

24. The hierarchical switch matrix of claim 22 wherein said plurality of output lines of another one of said plurality of programmable logic blocks is connected to a second group of lines in said multiplicity of input lines of said programmable segment switch matrix.

25. The hierarchical switch matrix of claim 22 wherein said multiplicity of bidirectional signal lines of said programmable global switch matrix comprises:

a second bidirectional bus; and

said programmable global switch matrix further comprises;

a plurality of programmable demultiplexers wherein each demultiplexer has an input terminal connected to a line in said first bidirectional bus;

a first output terminal connected to a line in said second bidirectional bus; and

a second output terminal connected to another line in said second bidirectional bus.

26. The hierarchical switch matrix of claim 22 wherein said multiplicity of bidirectional signal lines of said programmable global switch matrix comprises:

a second bidirectional bus; and

programmable global switch matrix further comprises;

a plurality of programmable demultiplexers wherein each demultiplexer has an input terminal connected to a line in said second bidirectional bus;

a first output terminal connected to a first line in said first bidirectional bus; and

a second output terminal connected to another line in said first bidirectional bus.

27. The hierarchical switch matrix of claim 22 wherein said programmable segment switch matrix comprises:

a programmable demultiplexer having an input terminal connected to a line in said multiplicity of programmable segment switch matrix input lines;

a first output terminal connected to a line in said first bidirectional bus; and

a second output terminal connected to another line in said first bidirectional bus.

28. The hierarchical switch matrix of claim 22 wherein said programmable block switch matrix comprises a plurality of programmable multiplexers with each programmable multiplexer having a plurality of input lines and an output line so that said plurality of programmable multiplexers have pluralities of input lines and a plurality of output lines;

and further wherein said multiplicity of output lines of said programmable block switch matrix includes said plurality of output lines of said plurality of programmable multiplexers and said multiplicity of input lines of said programmable block switch matrix includes said pluralities of input lines of said plurality of programmable multiplexers.

29. In a very high density programmable logic device, a hierarchical switch matrix comprising:

(i) a programmable block switch matrix having a multiplicity of input lines and a multiplicity of output lines;

wherein said programmable block switch matrix selectively connects and disconnects said multiplicity of input lines to said multiplicity of output lines; and

a signal path through said programmable block switch matrix, and one of a plurality of programmable logic blocks connected to said multiplicity of output lines of said programmable block switch matrix defines a first level of said hierarchical switch matrix and further wherein any other level of said hierarchical switch matrix includes said first level within said any other level; and

(ii) a programmable global switch matrix having a multiplicity of output lines and a multiplicity of input lines;

wherein said programmable global switch matrix selectively connects and disconnects said multiplicity of programmable switch matrix input lines to said multiplicity of programmable global switch matrix output lines;

said multiplicity of output lines of said programmable global switch matrix is coupled to said multiplicity of input lines of said programmable block switch matrix;

a set of input lines in said multiplicity of input lines of said programmable global switch matrix is connected to a plurality of output lines of said one of a plurality of programmable logic blocks so that signals from said one of said plurality of programmable logic blocks are provided to said programmable global switch matrix without passing through the programmable block switch matrix; and

another signal path through said programmable global switch matrix, said programmable block switch matrix, and said one of a plurality of programmable logic blocks defines another level of said hierarchical switch matrix so that said another level includes said first level.

30. The hierarchical switch matrix of claim 29 wherein a plurality of output lines of said one of said plurality of programmable logic circuits is connected to a first group of lines in said multiplicity of input lines of said programmable block switch matrix.

31. The hierarchical switch matrix of claim 29 wherein said multiplicity of output lines and said multiplicity of input lines of said programmable global switch matrix are a single multiplicity of bidirectional signal lines.

32. The hierarchical switch matrix of claim 29 wherein said programmable block switch matrix comprises a plurality of programmable multiplexers with each programmable multiplexer having a plurality of input lines and an output line so that said plurality of programmable multiplexers have pluralities of input lines and a plurality of output lines;

and further wherein said multiplicity of output lines of said programmable block switch matrix is said plurality of output lines of said plurality of programmable multiplexers and said multiplicity of input lines of said programmable block switch matrix is said pluralities of input lines of said plurality of programmable multiplexers.

33. The hierarchical switch matrix of claim 29 wherein said coupling of said multiplicity of output lines of said programmable global switch matrix to said multiplicity of input lines of said programmable block switch matrix is a direct connection of said multiplicity of output lines of said programmable global switch matrix to said multiplicity of input lines of said programmable block switch matrix.

34. In a very high density programmable logic device, a hierarchical switch matrix comprising:

(i) a programmable block switch matrix having a multiplicity of input lines and a multiplicity of output lines;

wherein said programmable block switch matrix selectively connects and disconnects said multiplicity of input lines to said multiplicity of output lines; and

a signal path through said programmable block switch matrix and one of a plurality of programmable logic circuits defines a first level of said hierarchical switch matrix and further wherein any other level of said hierarchical switch matrix includes said first level within said any other level; and

(ii) a programmable segment switch matrix having a multiplicity of output lines and a multiplicity of input lines;

wherein said programmable segment switch matrix selectively connects and disconnects said multiplicity of programmable segment switch matrix input lines to said multiplicity of programmable segment switch matrix output lines;

said multiplicity of output lines of said programmable segment switch matrix is connected to said multiplicity of input lines of said programmable block switch matrix;

a plurality of output lines of said one of said plurality of programmable logic circuits is connected to a group of lines in said multiplicity of input lines of said programmable segment switch matrix so that signals from said one of said plurality of programmable logic circuits are provided to said programmable segment switch matrix without passing through the programmable block switch matrix; and

another signal path through said programmable segment switch matrix, said programmable block switch matrix, and one of a plurality of programmable logic circuits defines another level of said hierarchical switch matrix so that said another level includes said first level.

35. The hierarchical switch matrix of claim 34 wherein a plurality of output lines of said one of said plurality of programmable logic circuits is connected to a first group of lines in said multiplicity of input lines of said programmable block switch matrix.

36. The hierarchical switch matrix of claim 34 wherein said programmable segment switch matrix comprises:

a bus; and

a programmable demultiplexer having an input terminal connected to a line in said multiplicity of programmable segment switch matrix input lines;

a first output terminal connected to a line in said bus; and

a second output terminal connected to another line in said bus.

37. The hierarchical switch matrix of claim 34 wherein said programmable block switch matrix comprises a plurality of programmable multiplexers with each programmable multiplexer having a plurality of input lines and an output line so that said plurality of programmable multiplexers have pluralities of input lines and a plurality of output lines;

and further wherein said multiplicity of output lines of said programmable block switch matrix is said plurality of output lines of said plurality of programmable multiplexers and said multiplicity of input lines of said programmable block switch matrix is said pluralities of input lines of said plurality of programmable multiplexers.

38. A method for interconnecting programmable logic blocks that is scalable from a CPLD having a first number of said programmable logic blocks to another CPLD having a second number of said programmable logic blocks comprising:

arranging said programmable logic blocks in a CPLD into segments wherein each segment includes a plurality of said programmable logic blocks;

interconnecting said plurality of programmable logic blocks in each segment to a programmable segment switch matrix;

wherein said programmable segment switch matrix in each segment is independent from said segment switch matrix in each of said other segments; and

said plurality of programmable logic blocks within said segment communicate only through said segment switch matrix; and

interconnecting each programmable segment switch matrix to a bi-directional bus of a programmable global switch matrix

wherein a programmable logic block in one segment communicates with a programmable logic block in another segment through said global switch matrix; and

another segment can be added to said CPLD without affecting other segments in said CPLD by interconnecting a segment switch matrix in said another segment to said bi-directional bus of said global switch matrix and so said method of interconnecting is scalable.

39. A method as in claim 38 wherein said operation of interconnecting each programmable segment switch matrix to a programmable global switch matrix further comprises:

connecting output terminals of a programmable demultiplexer to input lines of said programmable segment switch matrix; and

connecting an input terminal of said programmable demultiplexer to a line in a bi-directional bus of said programmable global switch matrix.

40. A method as in claim 38 wherein said operation of interconnecting said plurality of programmable logic blocks in each segment to a programmable segment switch matrix further comprises:

connecting an input terminal of a programmable demultiplexer to an output line of one of said programmable logic block;

connecting a first output terminal of said programmable demultiplexer to a line in a bus of said programmable segment switch matrix;

connecting a second output terminal of said programmable demultiplexer to another line in said bus of said programmable segment switch matrix.

41. A method as in claim 38 wherein said operation of interconnecting said plurality of programmable logic blocks in each segment to a programmable segment switch matrix further comprises:

arranging said programmable segment switch matrix in strips wherein each strip communicates with a different programmable logic block in said segment.