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Multi-tiered hierarchical high speed switch matrix structure for very high-density complex programmable logic devices

  • US 5,818,254 A
  • Filed: 06/02/1995
  • Issued: 10/06/1998
  • Est. Priority Date: 06/02/1995
  • Status: Expired due to Term
First Claim
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1. In an integrated circuit having a plurality of programmable logic circuits wherein each programmable logic circuit includes a plurality of input lines and a plurality of output lines, a programmable hierarchical switch matrix comprising:

  • (i) a first programmable switch matrix having a multiplicity of output lines and a multiplicity of input lines;

    wherein said first programmable switch matrix selectively connects and disconnects each line in said multiplicity of said programmable first switch matrix input lines to and from at least one line in said multiplicity of first programmable switch matrix output lines;

    said first programmable switch matrix output lines are connected to a plurality of input lines of one of said plurality of programmable logic circuits;

    and a signal path through said first programmable switch matrix and said one of said plurality of programmable logic circuits defines a first level of said hierarchical switch matrix;

    (ii) a second programmable switch matrix having;

    a multiplicity of programmable demultiplexers wherein each programmable demultiplexer has an input terminal and N output terminals, where N is an integer, and each programmable demultiplexer selectively connects said input terminal to one of said N output terminals and disconnects remaining output terminals of said N output terminals from said input terminal;

    a multiplicity of input lines wherein each input line is connected to one input terminal of one demultiplexer in said plurality of demultiplexers; and

    a multiplicity of output lines wherein each output line is connected to an output terminal of at least one demultiplexer in said plurality of demultiplexers;

    wherein a set of output lines in said multiplicity of said second programmable switch matrix output lines is coupled to a set of input lines in said multiplicity of said programmable first switch matrix input lines so that another signal path through said second programmable switch matrix, said first programmable switch matrix, and said one of said plurality of programmable logic circuits defines another level of said hierarchical switch matrix; and

    a set of output lines in a plurality of output lines of said one of said plurality of programmable logic circuits is coupled to a group of input lines in said multiplicity of input lines of said programmable second switch matrix so that a signal from said programmable logic circuit has a signal route to said second programmable switch matrix without passing through said first switch matrix.

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