Low power combinational logic circuit

• US 5,818,256 A
• Filed: 06/11/1996
• Issued: 10/06/1998
• Est. Priority Date: 04/19/1995
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation), Toshiba Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Usami, Kimiyoshi
• Primary Examiner(s): SANTAMAURO, JON P
• Application Number:
  US08/661,764
• Time in Patent Office: 847 Days
• Field of Search: 326/80-81, 326/62-63, 326/68, 326/21, 326/104, 326/121
• US Class Current: 326/80
• CPC Class Codes: H03K 19/0008 Arrangements for reducing power consumption

Abstract

The power consumption by a combinational logic circuit having primary input and output terminals is reduced. The constituent gates of the combinational logic are clustered in terms of the operating voltage levels thereof. First, the gates driven with the highest operating voltage are clustered just adjacent to the primary input terminals. Next, the gates driven with the next higher voltage are clustered adjacent to the primary input terminals only through the gates driven with the highest voltage, followed by repetition of the same clustering procedure in the order of the operating voltage level. Finally, the gates driven with the lowest operating voltage are clustered just adjacent to the primary output terminals.

Claims

1. A combinational logic circuit designed in a semiconductor integrated circuit and having at least one primary input terminal and at least one primary output terminal, comprising:

a plurality of first gates each of which has input and output nodes and is driven with a first operating voltage; and

a plurality of second gates each of which has input and output nodes and is driven with a second operating voltage which is lower than said first operating voltage, wherein any one of the output nodes of said second gates is connected only to either one of the input nodes of said second gates or one of the primary output terminals but not to any one of the input nodes of said first gates, and

a plurality of third gates each of which has input and output nodes and is driven with a third operating voltage which is lower than said first operating voltage but higher than said second operating voltage, wherein any one of the input nodes of said third gates is connected only to either one of the output nodes of said first gates or one of said primary input terminals but not to any one of the input nodes of said second gates.

2. A combinational logic circuit designed in a semiconductor integrated circuit and having a plurality of logic cells arranged in an array, the semiconductor integrated circuit including at least one primary input terminal and at least one primary output terminal, the combinational logic circuit comprising:

a plurality of first logic gates each of which is driven with a first operating voltage;

a plurality of second logic gates each of which is driven with a second operating voltage lower than said first operating voltage; and

a plurality of level converter circuits connected to said second logic gates for converting a level of said second operating voltage to said first operating voltage,

wherein any one of the output nodes of said second logic gates is connected only to either one of the input nodes of said second logic gates or the at least one primary output terminal, but not to any one of the input nodes of said first logic gates, and

wherein each level converter circuit is a level convertible latch circuit which is capable of holding a signal input thereto and converting a voltage level of the input signal from said second operating voltage to said first operating voltage.

3. The combinational logic circuit as claimed in claim 2, wherein said level convertible latch includes a latch circuit comprising a pair of inverters driven with said first operating power voltage and coupled to each other with an input node of each inverter connected to an output node of the other inverter, the input node of one of said inverters being connected to ground through a first transistor which is turned on and off in response to the signal input to said level convertible latch, the input node of the other of said inverters being connected to ground through a second transistor which is turned on and off in response to the signal input to said level convertible latch in an opposite manner to operation of said first transistor.