Dynamic circuit having improved noise immunity and method therefor

• US 5,818,264 A
• Filed: 12/17/1996
• Issued: 10/06/1998
• Est. Priority Date: 12/17/1996
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Mikan, Donald George Jr., Ciraula, Michael Kevin
• Primary Examiner(s): Santamauro, Jon
• Assistant Examiner(s): LE, DON P
• Application Number:
  US08/767,773
• Time in Patent Office: 658 Days
• Field of Search: 326/23, 326/24, 326/98, 326/83, 326/121, 326/95, 327/215, 327/218, 327/219, 327/333, 327/391
• US Class Current: 326/98
• CPC Class Codes: H03K 19/00361 in field effect transistor circuits

Abstract

A dynamic circuit has an improved noise margin that is not solely dominated by a threshold voltage of the transistors from which it is comprised. A transistor is utilized such that a ratio of the width of the feedback device to a pull-down transistor in a dynamic circuit determines when the pull-down transistor becomes active and conducts current. Therefore, rather than having a low threshold voltage which may be significantly and substantially impacted by the presence of noise on an input signal, beta ratioed transistors are implemented to give greater noise immunity and increase a circuit'"'"'s ability to tolerate noisy input lines. Furthermore, a structure of the dynamic circuit of the dynamic circuit preserves the functionality of that circuit. More specifically, after a dynamic node of a circuit of the present invention has been discharged, the node remains discharged and is only precharged again when a subsequent clock pulse occurs.

Claims

1. A dynamic circuit, comprising:

an input means for receiving an input signal, comprising;

a first transistor having a first electrode, a second electrode, and a control electrode coupled to the input signal;

a second transistor having a first electrode coupled to the second electrode of the first transistor, a second electrode, and a control electrode coupled to the input signal;

a clock means for receiving a clock signal, comprising;

a third transistor having a first electrode coupled to the second electrode of the second transistor, a second electrode coupled to a ground reference voltage, and a control electrode coupled to the clock signal;

a fourth transistor having a first electrode coupled to a first power reference voltage, a second electrode coupled to the second electrode of the first transistor, and a control electrode coupled to the clock signal; and

a feedback means for generating an output signal, comprising;

an inverter having an input coupled to the second electrode of the fourth transistor and an output for providing the output signal; and

a filth transistor having a first electrode coupled to a second power reference voltage, a second electrode coupled to a first electrode of the first transistor, and a control electrode coupled to the output of the inverter.

2. The dynamic circuit of claim 1 wherein a dynamic node of the dynamic circuit is a connection between the second electrode of the first transistor and the first electrode of the second transistor.

3. The dynamic circuit of claim 2 wherein the dynamic node is discharged to a first voltage level when the input signal has a second voltage level.

4. The dynamic circuit of claim 3 wherein a ratio between a width of the first transistor and a width of the third transistor determines the second voltage level.

5. A dynamic circuit, comprising:

an input means for receiving an input signal, comprising;

a first transistor having a first electrode, a second electrode, and a control electrode coupled to the input signal;

a second transistor having a first electrode coupled to the second electrode of the first transistor, a second electrode coupled to a first reference ground voltage, and a control electrode coupled to the input signal; and

a third transistor having a first electrode coupled to a first power reference voltage, a second electrode coupled to the first electrode of the first transistor, and a control electrode;

a clock means for receiving a clock signal, comprising;

a fourth transistor having a first electrode, a second electrode coupled to the second electrode of the first transistor, and a control electrode coupled to the clock signal;

a fifth transistor having a first electrode coupled to a second power reference voltage, a second electrode coupled to the first electrode of the fourth transistor, and a control electrode coupled to the clock signal; and

a feedback means for generating an output signal, comprising;

an inverter having an input coupled to the second electrode of the fifth transistor and an output coupled to the control electrode of the third transistor for providing the output signal; and

a sixth transistor having a first electrode coupled to a third power reference voltage, a second electrode coupled to a first electrode of the fourth transistor, and a control electrode coupled to the output of the inverter.

6. The dynamic circuit of claim 5 wherein the dynamic circuit performs a logical AND function.

7. A dynamic circuit, comprising:

an input means for receiving an input signal, comprising;

a first transistor having a first electrode, a second electrode, and a control electrode coupled to the input signal;

a second transistor having a first electrode coupled to the second electrode of the first transistor, a second electrode coupled to a first reference ground voltage, and a control electrode coupled to the input signal; and

a third transistor having a first electrode coupled to a first power reference voltage, a second electrode coupled to the first electrode of the first transistor, and a control electrode,

a clock means for receiving a clock signal, comprising;

a fourth transistor having a first electrode coupled to a second power reference voltage, and a control electrode coupled to the clock signal, and

a feedback means for generating an output signal, comprising;

an inverter having an input coupled to a second electrode of the fourth transistor and an output coupled to the control electrode of the third transistor for providing the output signal; and

a fifth transistor having a first electrode coupled to a third power reference voltage, a second electrode coupled to the input of the inverter, and

a control electrode coupled to the output of the inverter; and

a sixth transistor having a first electrode coupled to the input of the inverter, a second electrode coupled to the first electrode of the second transistor and a control electrode coupled to the clock signal.