Temperature balanced circuit

• US 5,818,277 A
• Filed: 01/28/1997
• Issued: 10/06/1998
• Est. Priority Date: 01/28/1997
• Status: Expired due to Fees

• Current Assignee: Advantest Corporation
• Original Assignee: Advantest Corporation
• Inventors: Miura, Takeo
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): Wells, Kenneth B.
• Application Number:
  US08/790,228
• Time in Patent Office: 616 Days
• Field of Search: 327/262, 327/265, 327/273, 327/276, 327/277, 327/279, 327/284, 327/286, 327/160, 327/161, 327/512, 327/513
• US Class Current: 327/262
• CPC Class Codes: H03K 5/135 by the use of time reference signals, e.g. clock signals

Abstract

A temperature balanced circuit is provided which is capable of, in case a CMOS•IC is utilized as a delay circuit, giving a constant delay time to an input signal to the delay circuit even if the frequency of the input signal is varied. A delay circuit 11 and a dummy circuit 11 having the same construction as that of the delay circuit are provided in a CMOS•IC. There are provided a counter counting first pulse signals CP1 supplied to the delay circuit during a fixed time interval and arithmetic unit finding a difference between a count value of this counter and a predetermined value, and the same number of second pulse signals as the difference value found by the arithmetic unit is supplied to the dummy circuit, thereby to define to a constant value both the number of the first pulses and the number of the second pulses supplied to the CMOS•IC within a unit time interval, which results in uniformity of an amount of heat generated in the CMOS•IC.

Claims

1. A temperature balanced circuit comprising:

a delay circuit giving a predetermined delay time to an input signal and outputting the delayed signal;

a first pulse supply path connected to said delay circuit and supplying a first pulse signal to be delayed to said delay circuit;

a second pulse supply path supplying a second pulse signal having a frequency equal to or higher than that of the first pulse signal supplied from said first pulse supply path;

a counter counting the number of said first pulse signals within a predetermined fixed time interval;

arithmetic means for finding a difference value between a count value of said counter and a predetermined value;

pulse extracting means, coupled to the arithmetic means, for taking out the same number of the second pulse signals as said difference value found by said arithmetic means; and

a dummy circuit supplied with the second pulses taken out by said pulse extracting means and provided near said delay circuit, said dummy circuit having the same construction as that of said delay circuit.

2. The temperature balanced circuit according to claim 1, wherein said arithmetic means comprises a presettable counter which operates to find a difference between a full counter value of the presettable counter and the count value of said counter read from said counter.

3. The temperature balanced circuit according to claim 1 wherein said delay circuit and said dummy circuit are formed as one semiconductor integrated circuit.

4. The temperature balanced circuit according to claim 3 wherein said semiconductor integrated circuit is a CMOS•

IC.

5. The temperature balanced circuit according to claim 1, further comprising timer means for controlling the counter such that said counter counts the first pulse signals for a constant time interval.

6. The temperature balanced circuit according to claim 5, wherein said timer means comprises:

a second counter connected to said second pulse supply path; and

a logic circuit logically controlling the output of said second counter, and wherein said timer means causes said counter counting the first pulse signals to perform a counting operation during the constant time interval from the time that said counter of said timer means connected to said second pulse supply path starts to count the second pulse signals to the time that said counter of said timer means connected to said second pulse supply path reaches its full count value.

7. The temperature balanced circuit according to claim 5, wherein said timer means comprises:

a counter connected to said second pulse supply path; and

a logic circuit logically controlling the output of said counter of said timer means, and

wherein the count value of said counter counting the first pulse signals is received in said arithmetic means when said counter of said timer means connected to said second pulse supply path reaches its full count value.