Level shift circuit

• US 5,818,278 A
• Filed: 03/03/1997
• Issued: 10/06/1998
• Est. Priority Date: 09/06/1996
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Yamamoto, Kazuya, Maemura, Kousei
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): LAM, TUAN THIEU
• Application Number:
  US08/805,883
• Time in Patent Office: 582 Days
• Field of Search: 327/333, 327/331, 327/306, 326/63, 326/69, 326/80, 326/68, 326/81, 326/83
• US Class Current: 327/333
• CPC Class Codes: H03K 19/018514 with at least one differential stage H03K19/018528 and H03K19/018542 take precedence
• CPC Class Codes: H03K 3/356034 the input circuit having a differential configuration

Abstract

A level shift circuit shifting logic levels of an SCFL circuit to logic levels of a DCFL circuit, including an SCFL circuit having complementary outputs; two source follower circuits with their inputs respectively connected to the complementary outputs of the SCFL circuit; a high/low detecting circuit detecting "high" or "low" signals which have DCFL levels from the two source follower circuits and outputting signals having logic levels according to the detection results; and DCFL circuits with inputs connected to outputs of the high/low detecting circuit. Therefore, it is possible to obtain a level shift circuit operating with a wider voltage range and in a wider temperature range than the prior art circuit.

Claims

1. A level shift circuit shifting logic levels of an SCFL circuit to logic levels of a DCFL circuit comprising:

an SCFL circuit having two complementary outputs;

a DCFL type flip-flop circuit comprising two series circuits, each series circuit including a switching FET and a load resistor, two parallel circuits, each parallel circuit having a resistor and a capacitance, and two input/output nodes connected to connection nodes of the switching FETs and the load resistors in the two series circuits, wherein the two input/output nodes are cross-coupled to gates of the switching FETs of the two series circuits through the two parallel circuits;

two source follower circuits, each source follower circuit comprising an FET and a diode and having inputs connected to the complementary outputs of the SCFL circuit and outputs connected to the load resistors of the series circuits, the load resistors being connected to the switching FETs; and

two DCFL circuits having inputs connected to the two input/output nodes and at least one output connected to a following stage DCFL circuit.

2. The level shift circuit as defined in claim 1 wherein the respective capacitances are removed from the two parallel circuits.

3. The level shift circuit as defined in claim 1 wherein the respective load resistors are removed from the two series circuits.

4. The level shift circuit as defined in claim 1 wherein the respective diodes are removed from the two source follower circuits.

5. A level shift circuit shifting logic levels of an SCFL circuit to logic levels of a DCFL circuit comprising:

an SCFL circuit having two complementary outputs;

two source follower circuits having inputs respectively connected to corresponding complementary outputs of the SCFL circuit;

a flip-flop circuit detecting "high" or "low" signals that have reached a DCFL level, through the two source follower circuits, and outputting output signals at two complementary outputs that have logic levels set in response to detection results produced by the flip-flop circuit; and

DCFL circuits having respective inputs connected to corresponding outputs of the high/low detecting circuit.

6. The level shift circuit as defined in claim 5 wherein the flip-flop circuit comprises two series circuits, each series circuit including a switching FET and a load resistor, two parallel circuits, each parallel circuit having a resistor and a capacitor, and two input/output nodes connected to connection nodes of the switching FET'"'"'s and the load resistors in the two series circuits, wherein the two input/output nodes are cross-coupled to gates of the switching FET'"'"'s of the two series circuits through the two parallel circuits.