Bipolar element averaging, digital-to-analog converter

• US 5,818,377 A
• Filed: 04/15/1997
• Issued: 10/06/1998
• Est. Priority Date: 04/15/1997
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Wieser, James Brian
• Primary Examiner(s): Young, Brain K.
• Application Number:
  US08/842,658
• Time in Patent Office: 539 Days
• Field of Search: 341/144, 341/143, 341/145, 341/150, 341/152
• US Class Current: 341/144
• CPC Class Codes: H03M 1/0665 using data dependent selection of the elements, e.g. data weighted averaging
• CPC Class Codes: H03M 1/806 with equally weighted capacitors which are switched by unary decoded digital signals
• CPC Class Codes: H03M 3/464 Details of the digital/analogue conversion in the feedback path
• CPC Class Codes: H03M 3/502 Details of the final digital/analogue conversion following the digital delta-sigma modulation

Abstract

A bipolar, element averaging, digital to analog signal converter including a delta-sigma digital to analog converter (".increment.Σ DAC") with dual sequence controllers for controlling the switching sequences of the array of sampling capacitors used to sample a fixed reference voltage in the sample and hold amplifier. The sequence controllers receive the input digital signal and a sign bit which indicates whether the numeric value of the digital signal is positive or negative with respect to the mean value of its total dynamic range. Based upon the sign bit and the value of the digital signal, the sequence controllers generate two sets of switching sequence control signals: "positive" and "negative." Those digital signals whose numeric values are positive and negative with respect to the mean value are considered to be "positive" and "negative" signals, respectively, with corresponding positive and negative analog signals generated accordingly. The same capacitors in the sampling array are used in rotating sequences for sampling the reference voltage for both "positive" and "negative" input digital signals. The "positive" and "negative" switching sequence control signal sets each ensure that each capacitor in the sampling array is used a substantially equal number of times when converting "positive" and "negative" input digital signals. Such a converter can be used in digital to analog converters as well as analog to digital converters which use delta-sigma signal conversion techniques.

Claims

1. An apparatus including a bipolar, element averaging, digital to analog signal converter, comprising:

a sampling controller configured to receive a multiple bit digital signal and a sign signal and in accordance therewith provide a plurality of sampling control signals, wherein

said multiple bit digital signal includes a plurality of digital magnitudes representing a plurality of numeric values having a mean value associated therewith,

said sign signal indicates whether a corresponding one of said plurality of numeric values represented by said multiple bit digital signal is positive or negative with respect to said mean value; and

a plurality of sampling circuits, coupled to said sampling controller, configured to receive said plurality of sampling control signals and in accordance therewith sample a reference signal and in accordance therewith provide an analog signal which corresponds to said multiple bit digital signal and includes a plurality of analog magnitudes representing said plurality of numeric values;

wherein, in accordance with said plurality of sampling control signals, each one of said plurality of sampling circuits is used to sample said reference signal

a first substantially equal number of times when, in accordance with said sign signal, each one of said plurality of numeric values represented by said multiple bit digital signal is positive with respect to said mean value, and

a second substantially equal number of times when, in accordance with said sign signal, each one of said plurality of numeric values represented by said multiple bit digital signal is negative with respect to said mean value.

2. The apparatus of claim 1, wherein:

said plurality of sampling control signals represents a first rotating sequence when said sign signal indicates that a corresponding one of said plurality of numeric values represented by said multiple bit digital signal is positive with respect to said mean value; and

said plurality of sampling control signals represents a second rotating sequence when said sign signal indicates that a corresponding one of said plurality of numeric values represented by said multiple bit digital signal is negative with respect to said mean value.

3. The apparatus of claim 1, wherein, in accordance with said plurality of sampling control signals, each one of said plurality of sampling circuits is used to sample said reference signal:

successively in a first rotating sequence when, in accordance with said sign signal, each one of said plurality of numeric values represented by said multiple bit digital signal is positive with respect to said mean value; and

successively in a second rotating sequence when, in accordance with said sign signal, each one of said plurality of numeric values represented by said multiple bit digital signal is negative with respect to said mean value.

4. The apparatus of claim 1, wherein said sampling controller comprises:

a first sequence controller circuit configured to receive said multiple bit digital signal and said sign signal and in accordance therewith provide a first plurality of sampling sequence signals;

a second sequence controller circuit configured to receive said multiple bit digital signal and said sign signal and in accordance therewith provide a second plurality of sampling sequence signals; and

a plurality of switch circuits, coupled to said first and second sequence controller circuits, configured to receive said sign signal and in accordance therewith receive and select between said first and second pluralities of sampling sequence signals and in accordance therewith provide said selected one of said first and second pluralities of sampling sequence signals as said plurality of sampling control signals.

5. The apparatus of claim 4, wherein:

said first plurality of sampling sequence signals represents a first rotating sequence when said sign signal indicates that a corresponding one of said plurality of numeric values represented by said multiple bit digital signal is positive with respect to said mean value; and

said second plurality of sampling sequence signals represents a second rotating sequence when said sign signal indicates that a corresponding one of said plurality of numeric values represented by said multiple bit digital signal is negative with respect to said mean value.

6. The apparatus of claim 1, wherein said plurality of sampling circuits comprises:

a reference node configured to receive said reference signal;

a plurality of capacitive circuits; and

a plurality of switch circuits, coupled between said reference node and said plurality of capacitive circuits, configured to receive said plurality of sampling control signals and in accordance therewith electrically couple and decouple portions of said plurality of capacitive circuits to and from said reference node, respectively;

wherein said electrically coupled and decoupled portions of said plurality of capacitive circuits together provide said analog signal.

7. The apparatus of claim 6, further comprising an integrator circuit, coupled to said plurality of capacitive circuits, configured to receive and integrate said analog signal.

8. The apparatus of claim 7, wherein said plurality of sampling circuits and said integrator circuit together comprise a sample and hold amplifier.

9. The apparatus of claim 6, further comprising a low pass filter circuit, coupled to said plurality of capacitive circuits, configured to receive and low pass filter said analog signal.

10. An apparatus including a bipolar, element averaging, digital to analog signal converter, comprising:

a sampling controller configured to receive a multiple bit digital signal and a sign signal and in accordance therewith provide a plurality of sampling control signals, wherein

said multiple bit digital signal includes a plurality of digital magnitudes representing a plurality of numeric values having a mean value associated therewith,

said sign signal indicates whether a corresponding one of said plurality of numeric values represented by said multiple bit digital signal is positive or negative with respect to said mean value; and

a plurality of sampling circuits, coupled to said sampling controller, configured to receive said plurality of sampling control signals and in accordance therewith sample a reference signal and in accordance therewith provide an analog signal which corresponds to said multiple bit digital signal and includes a plurality of analog magnitudes representing said plurality of numeric values;

wherein, in accordance with said plurality of sampling control signals, each one of said plurality of sampling circuits is used to sample said reference signal

successively in a first rotating sequence when, in accordance with said sign signal, each one of said plurality of numeric values represented by said multiple bit digital signal is positive with respect to said mean value, and

successively in a second rotating sequence when, in accordance with said sign signal, each one of said plurality of numeric values represented by said multiple bit digital signal is negative with respect to said mean value.

11. The apparatus of claim 10, wherein:

said plurality of sampling control signals represents said first rotating sequence when said sign signal indicates that a corresponding one of said plurality of numeric values represented by said multiple bit digital signal is positive with respect to said mean value; and

said plurality of sampling control signals represents said second rotating sequence when said sign signal indicates that a corresponding one of said plurality of numeric values represented by said multiple bit digital signal is negative with respect to said mean value.

12. The apparatus of claim 10, wherein said sampling controller comprises:

a first sequence controller circuit configured to receive said multiple bit digital signal and said sign signal and in accordance therewith provide a first plurality of sampling sequence signals;

a second sequence controller circuit configured to receive said multiple bit digital signal and said sign signal and in accordance therewith provide a second plurality of sampling sequence signals; and

a plurality of switch circuits, coupled to said first and second sequence controller circuits, configured to receive said sign signal and in accordance therewith receive and select between said first and second pluralities of sampling sequence signals and in accordance therewith provide said selected one of said first and second pluralities of sampling sequence signals as said plurality of sampling control signals.

13. The apparatus of claim 12, wherein:

said first plurality of sampling sequence signals represents said first rotating sequence when said sign signal indicates that a corresponding one of said plurality of numeric values represented by said multiple bit digital signal is positive with respect to said mean value; and

said second plurality of sampling sequence signals represents said second rotating sequence when said sign signal indicates that a corresponding one of said plurality of numeric values represented by said multiple bit digital signal is negative with respect to said mean value.

14. The apparatus of claim 10, wherein said plurality of sampling circuits comprises:

a reference node configured to receive said reference signal;

a plurality of capacitive circuits; and

a plurality of switch circuits, coupled between said reference node and said plurality of capacitive circuits, configured to receive said plurality of sampling control signals and in accordance therewith electrically couple and decouple portions of said plurality of capacitive circuits to and from said reference node, respectively;

wherein said electrically coupled and decoupled portions of said plurality of capacitive circuits together provide said analog signal.

15. The apparatus of claim 14, further comprising an integrator circuit, coupled to said plurality of capacitive circuits, configured to receive and integrate said analog signal.

16. The apparatus of claim 15, wherein said plurality of sampling circuits and said integrator circuit together comprise a sample and hold amplifier.

17. The apparatus of claim 14, further comprising a low pass filter circuit, coupled to said plurality of capacitive circuits, configured to receive and low pass filter said analog signal.

18. A method of performing a bipolar, element averaging, digital to analog signal conversion, comprising the steps of:

receiving a multiple bit digital signal and a sign signal and in accordance therewith generating a plurality of sampling control signals, wherein

said multiple bit digital signal includes a plurality of digital magnitudes representing a plurality of numeric values having a mean value associated therewith,

said sign signal indicates whether a corresponding one of said plurality of numeric values represented by said multiple bit digital signal is positive or negative with respect to said mean value; and

sampling a reference signal in accordance with said plurality of sampling control signals and in accordance therewith generating an analog signal which corresponds to said multiple bit digital signal and includes a plurality of analog magnitudes representing said plurality of numeric values;

wherein, in accordance with said plurality of sampling control signals, said reference signal is sampled

a first substantially equal number of times when, in accordance with said sign signal, each one of said plurality of numeric values represented by said multiple bit digital signal is positive with respect to said mean value, and

a second substantially equal number of times when, in accordance with said sign signal, each one of said plurality of numeric values represented by said multiple bit digital signal is negative with respect to said mean value.

19. The method of claim 18, wherein said step of sampling a reference signal in accordance with said plurality of sampling control signals and in accordance therewith generating an analog signal comprises sampling, in accordance with said plurality of sampling control signals, said reference signal:

successively in a first rotating sequence when, in accordance with said sign signal, each one of said plurality of numeric values represented by said multiple bit digital signal is positive with respect to said mean value; and

successively in a second rotating sequence when, in accordance with said sign signal, each one of said plurality of numeric values represented by said multiple bit digital signal is negative with respect to said mean value.

20. The method of claim 18, wherein said step of receiving a multiple bit digital signal and a sign signal and in accordance therewith generating a plurality of sampling control signals comprises:

receiving said multiple bit digital signal and said sign signal and in accordance therewith generating first and second pluralities of sampling sequence signals; and

receiving said sign signal and in accordance therewith receiving and selecting between said first and second pluralities of sampling sequence signals and in accordance therewith outputting said selected one of said first and second pluralities of sampling sequence signals as said plurality of sampling control signals.

21. The method of claim 18, wherein said step of sampling a reference signal in accordance with said plurality of sampling control signals and in accordance therewith generating an analog signal comprises receiving said plurality of sampling control signals and in accordance therewith electrically charging, with said reference signal, and discharging portions of a plurality of capacitive circuits to provide said analog signal.

22. The method of claim 21, further comprising the step of integrating said analog signal.

23. The method of claim 21, further comprising the step of low pass filtering said analog signal.

24. A method of performing a bipolar, element averaging, digital to analog signal conversion, comprising the steps of:

receiving a multiple bit digital signal and a sign signal and in accordance therewith generating a plurality of sampling control signals, wherein

said multiple bit digital signal includes a plurality of digital magnitudes representing a plurality of numeric values having a mean value associated therewith,

said sign signal indicates whether a corresponding one of said plurality of numeric values represented by said multiple bit digital signal is positive or negative with respect to said mean value; and

sampling a reference signal in accordance with said plurality of sampling control signals and in accordance therewith generating an analog signal which corresponds to said multiple bit digital signal and includes a plurality of analog magnitudes representing said plurality of numeric values;

wherein, in accordance with said plurality of sampling control signals, said reference signal is sampled

successively in a first rotating sequence when, in accordance with said sign signal, each one of said plurality of numeric values represented by said multiple bit digital signal is positive with respect to said mean value, and

successively in a second rotating sequence when, in accordance with said sign signal, each one of said plurality of numeric values represented by said multiple bit digital signal is negative with respect to said mean value.

25. The method of claim 24, wherein said step of receiving a multiple bit digital signal and a sign signal and in accordance therewith generating a plurality of sampling control signals comprises:

receiving said multiple bit digital signal and said sign signal and in accordance therewith generating first and second pluralities of sampling sequence signals; and

receiving said sign signal and in accordance therewith receiving and selecting between said first and second pluralities of sampling sequence signals and in accordance therewith outputting said selected one of said first and second pluralities of sampling sequence signals as said plurality of sampling control signals.

26. The method of claim 24, wherein said step of sampling a reference signal in accordance with said plurality of sampling control signals and in accordance therewith generating an analog signal comprises receiving said plurality of sampling control signals and in accordance therewith electrically charging, with said reference signal, and discharging portions of a plurality of capacitive circuits to provide said analog signal.

27. The method of claim 26, further comprising the step of integrating said analog signal.

28. The method of claim 26, further comprising the step of low pass filtering said analog signal.