Active matrix substrate and manufacturing method of the same

• US 5,818,549 A
• Filed: 03/03/1997
• Issued: 10/06/1998
• Est. Priority Date: 04/26/1996
• Status: Expired due to Term

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Maruyama, Yuko, Kanemori, Yuzuru
• Primary Examiner(s): Sikes, William L.
• Assistant Examiner(s): TON, MINH TOAN T
• Application Number:
  US08/810,385
• Time in Patent Office: 582 Days
• Field of Search: 349/42, 349/139, 257/59
• US Class Current: 349/42
• CPC Class Codes: G02F 1/136204 Arrangements to prevent high voltage or static electricity failures
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body

Abstract

First and second gate insulating films, a semiconductor layer made of a-Si(i), and an etching stopper layer are formed to cover a gate electrode on a glass substrate. A drain electrode side contact layer and a source electrode side contact layer are made out of a-Si(n⁺) in such a manner to be cut off on the etching stopper layer. A disconnection preventing a-Si(n⁺) wire is formed below a source wire in its longitudinal direction, and atop of which a pixel electrode is formed. Since the disconnection preventing a-Si(n⁺) wire and source electrode side contact layer are spaced apart, static-induced characteristics deterioration of TFT and the point and line defects during the substrate fabrication sequence can be eliminated and the non-defective ratio of the display device can be improved drastically.

Claims

1. An active matrix substrate comprising:

a plurality of scanning lines and a plurality of signal lines intersecting each other,

n⁺ wires made of n⁺ -type semiconductor, said each n⁺ wire being provided below and along said each signal line, respectively; and

switching elements respectively provided to each intersection of said scanning lines and signal lines, said each switching element including a contact layer made of n⁺ -type semiconductor out of which said n⁺ wires are made,

wherein said contact layer and said each n⁺ wire are provided in such a manner to keep a space therebetween.

2. The active matrix substrate as defined in claim 1, wherein said space between said contact layer and said each n⁺ wire is in a range between 1 μ

m and 4 μ

m inclusive.

3. The active matrix substrate as defined in claim 1, wherein said space between said contact layer and said each n⁺ wire is in a range between 3 μ

m and 4 μ

m inclusive.

4. The active matrix substrate as defined in claim 1, wherein said switching elements are provided respectively on said scanning lines in a vicinity of each intersection of said scanning lines and signal lines.

5. A method of manufacturing an active matrix substrate comprising at least a plurality of scanning lines and a plurality of signal lines intersecting with said scanning lines, and switching elements each having a contact layer and provided near each intersection of said scanning lines and signal lines, respectively, said method comprising the steps of:

forming said each contact layer out of n⁺ -type semiconductor; and

forming an n⁺ wire out of n⁺ -type semiconductor below and along said each signal line in such a manner to keep a space from said each contact layer.

6. The method of manufacturing an active matrix substrate as defined in claim 5, wherein said predetermined space is in a range between 1 μ

m and 4 μ

m inclusive.

7. The method of manufacturing an active matrix substrate as defined in claim 5, wherein said predetermined space is in a range between 3 μ

m and 4 μ

m inclusive.