System and method for determining acceptable logic cell locations and generating a legal location structure

• US 5,818,726 A
• Filed: 03/06/1996
• Issued: 10/06/1998
• Est. Priority Date: 04/18/1994
• Status: Expired due to Term

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Lee, Tsu-Chang
• Primary Examiner(s): Voeltz, Emanuel Todd
• Assistant Examiner(s): Kik, Phallaka
• Application Number:
  US08/611,502
• Time in Patent Office: 944 Days
• Field of Search: 364/578, 364/468-491, 395/325, 371/22.2, 341/51, 358/133
• US Class Current: 716/112
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

A system and method for testing the placement of logic circuits on a regularly repeated array of integrated devices includes a base array memory, a basis memory, a floor plan memory, an array class memory, a logic cell index memory, a legal location index map memory, a legal location table memory and an engine. The system creates an array class for each type of device that is fabricated on the base array. The engine then tests each location of a basis of each array class for the legality of placing each logic cell of an associated group at that location. The engine then constructs a map of the array class, the legal location index map. Each entry on the map corresponds to a location in the array class, and each entry on the map contains a reference to a bit pattern. The engine also constructs a legal location table. The legal location table is a set of unique bit patterns that indicate the logic cells that may be placed at a location. The entries on the legal location index map reference bit patterns on the legal location table.

Claims

1. A method for testing placement of representations of physical implementations of a plurality of logic cells on a base array having a plurality of types of transistor-level devices, each of the transistor-level devices in a predetermined location on the base array, each representation of a physical implementation of a logic cell including at least one transistor-level device, the method comprising the steps of:

identifying a first type of transistor-level device on the base array corresponding to a predetermined position in a representation of a physical implementation of a first logic cell;

identifying a group of transistor-level representations of physical implementations of logic cells wherein said first type of transistor-level device is in a predetermined position in each representation of a physical implementation of a logic cell in said group;

building an array class comprising a group of locations disposed on the base array, each location in the array class having said first type of transistor-level device in the predetermined position in each representation of a physical implementation of a logic cell of the identified group;

determining whether a transistor-level representation of a physical implementation of a logic cell in the identified group of transistor-level representations of physical implementations of logic cells can be placed at a location in the array class; and

constructing a bit pattern for each location in the array class, each bit pattern indicating the representations of physical implementations of logic cells that can be placed at the location in the array class.

2. The method of claim 1, wherein the steps of identifying a first type of transistor-level device, identifying a group, building, determining, and constructing are repeated for each type of transistor-level device on the base array.

3. The method of claim 1, wherein the step of determining is performed for each transistor-level representation of a physical implementation of a logic cell in the identified group for locations in a basis of the base array;

and wherein the step of constructing is performed for each transistor-level representation of a physical implementation of a logic cell in the identified group for the locations in the basis of the base array.

4. The method of claim 1, wherein the steps of determining and constructing are executed for the locations within a predetermined distance of the boundaries of the base array.

5. The method of claim 1, wherein the steps of determining and constructing are executed for the locations occupied by a pre-existing structure on the base array, and for locations within a predetermined distance of the pre-existing structure on the base array.

6. The method of claim 1, wherein the step of identifying a group of transistor-level representations of physical implementations of logic cells comprises the steps of:

generating possible orientations of each transistor-level representation of a physical implementation of a logic cell;

separating a group of transistor-level representations of physical implementations of logic cells, from said possible orientations of each said transistor-level representation of a physical implementation of a logic cell, wherein each transistor-level representation of a physical implementation of a logic cell in this group has the same type of transistor-level device in the pre-determined position; and

combining the transistor-level representations of physical implementations of logic cells within the separated group that are the same size and shape to produce a master cache.

7. The method of claim 6, wherein the pre-determined position is the lower, left position of a transistor-level representation of a physical implementation of a logic cell.

8. The method of claim 6, wherein when transistor-level representations of physical implementations of logic cells within a group are combined, representations of physical implementations of internal wiring of said transistor-level representations of physical implementations of logic cells is combined in the master cache.

9. The method of claim 1, wherein the step of determining whether a transistor-level representation of a physical implementation of a logic cell in the identified group of transistor-level representations of physical implementations of logic cells can be placed at a location in the array class includes at least one of the following steps:

determining if the transistor-level devices that surround the location match the transistor-level devices of said transistor-level representation of a physical implementation of the logic cell;

comparing the transistor-level devices that surround the location with the transistor-level devices in said transistor-level representation of a physical implementation of the logic cell to determine if the transistor-level devices that surround the location are available for use by said representation of a physical implementation of the logic cell; and

determining if placing said transistor-level representation of a physical implementation of the logic cell at the location violates a design rule.

10. The method of claim 6, wherein the step of generating possible orientations of a transistor-level representation of a physical implementation of a logic cell comprises the step of transposing the transistor-level representation of a physical implementation of the logic cell through its x-axis.

11. The method of claim 6, wherein the step of generating possible orientations of a transistor-level representation of a physical implementation of a logic cell comprises the step of transposing the transistor-level representation of a physical implementation of the logic cell through its y-axis.

12. The method of claim 6, wherein the step of generating possible orientations of a transistor-level representation of a physical implementation of a logic cell comprises the step of transposing the transistor-level representation of a physical implementation of the logic cell through its x-axis and its y-axis.

13. The method of claim 6, wherein the step of generating possible orientations of a transistor-level representation of a physical implementation of a logic cell comprises the step of rotating the transistor-level representation of a physical implementation of the logic cell 180 degrees.

14. The method of claim 6, wherein the step of generating possible orientations of a transistor-level representation of a physical implementation of a logic cell comprises the step of rotating the transistor-level representation of a physical implementation of the logic cell 270 degrees.

15. The method of claim 1, further comprising the steps of:

eliminating duplicate bit patterns; and

constructing a table of the remaining, unique bit patterns.

16. The method of claim 15, further comprising the step of constructing a legal location index map of the array class including, for each location in the array class, a reference to a bit pattern in the table of unique bit patterns that identifies the transistor-level representation of a physical implementation of logic cells that can be placed at that location.

17. The method of claim 16, further comprising the steps of:

determining a region along a boundary of the base array;

determining if the transistor-level representations of physical implementations of logic cells of the identified group may be placed at the locations of the array class within the region;

adding bit patterns to the table of unique bit patterns for the locations of the array class within the region; and

altering the legal location index map for each location in the region to store the bit pattern that identifies the transistor-level representations of physical implementations of logic cells that can be placed at each respective location in the region.

18. The method of claim 17, wherein the step of determining the region along the boundary of the base array comprises the steps of:

selecting a first transistor-level representation of a physical implementation of a logic cell from the identified group of transistor-level representations of physical implementations of logic cells that is the largest transistor-level representation of a physical implementation of a logic cell in a vertical dimension;

determining a size of the first transistor-level representation of a physical implementation of a logic cell in the vertical dimension in terms of transistor-level devices;

subtracting one transistor-level device from the size of the first transistor-level representation of a physical implementation of a logic cell in the vertical dimension;

identifying rows of locations along an upper boundary of the base array wherein the number of rows is equal to the result of the subtracting step;

selecting a second transistor-level representation of a physical implementation of a logic cell from the group of representations of physical implementations of logic cells that is the largest transistor-level representation of a physical implementation of a logic cell in a horizontal dimension;

determining the size in the horizontal dimension of the second transistor-level representation of a physical implementation of a logic cell in terms of transistor-level devices;

subtracting one transistor-level from the size of the second transistor-level representation of a physical implementation of a logic cell in the horizontal dimension; and

identifying the columns of locations along a right boundary of the base array wherein the number of columns is equal to the result of the second subtracting step.

19. The method of claim 16, further comprising the steps of:

determining a region surrounding and occupied by a pre-existing structure on the base array;

determining the transistor-level representations of physical implementations of logic cells of the identified group that can be placed at the locations of the array class within the region;

adding bit patterns to the table, the bit patterns identifying the transistor-level representations of physical implementations of logic cells that can be placed at each location in the region; and

altering the map for each location in the region with the bit patterns that specify the transistor-level representations of physical implementations of logic cells that can be placed at the respective location in the region.

20. The method of claim 19, wherein the step of determining a region surrounding a pre-existing structure on the base array comprises the steps of:

identifying locations of the base array over the pre-existing structure;

selecting a first transistor-level representation of a physical implementation of a logic cell from the group of transistor-level representations of physical implementations of logic cells that is the largest transistor-level representation of a physical implementation of a logic cell in a vertical dimension;

determining the size in the vertical dimension of the first transistor-level representation of a physical implementation of a logic cell in terms of transistor-level devices;

first reducing the size of the first transistor-level representation of a physical implementation of a logic cell by one transistor-level device;

identifying rows of locations above and below the pre-existing structure on the base array wherein the number of rows is equal to the result of first reducing step in the vertical dimension;

selecting a second transistor-level representation of a physical implementation of a logic cell from the group of representations of physical implementations of logic cells that is the largest transistor-level representation of a physical implementation of a logic cell in a horizontal dimension;

determining a horizontal size of the second transistor-level representation of a physical implementation of a logic cell in terms of transistor-level devices;

second reducing the horizontal size of the second transistor-level representation of a physical implementation of a logic cell by one; and

identifying the columns of locations along left and right sides of the pre-existing structure on the base array wherein the number of columns is equal to the second reducing step in the horizontal dimension.

35. The method of claim 1, wherein each transistor-level device is not automatically identified with one of said logic cells.

21. A method for determining the legality of placing a transistor-level representation of a physical implementation of a logic cell at a location on a base array, the base array having a plurality of types of transistor-level devices, each of the transistor-level devices in a predetermined location on the base array, the method comprising the steps of:

identifying an input base array, an input location on the input base array, and a transistor-level representation of a physical implementation of an input logic cell;

determining an array class with a transistor-level device type corresponding to the input logic cell;

determining a type of transistor-level device at the input location;

determining if the type of transistor-level device at the identified location matches the transistor-level device type for the array class;

signaling that the input logic cell cannot be placed at the location if the type of transistor-level device at the identified location does not match the transistor-level device type for the array class; and

if the type of transistor-level device at the identified location matches the transistor-level device type for the array class performing the steps of;

determining a master cache to which the input logic cell corresponds;

retrieving a location table and a location map for the array class;

determining the bit pattern for the location using the location map and the location table and extracting a bit identifying whether the input logic cell can be placed at the input location;

determining if the extracted bit is high;

signaling that the input logic cell cannot be placed at the location if the bit is not high; and

signaling that the input logic cell can be placed at the location if the bit is high.

36. The method of claim 21, wherein each transistor-level device is not automatically identified with one of said logic cells.

22. An apparatus for creating a location table and location map for use in testing the placement of representations of physical implementations of logic cells on a base array of transistor-level devices, the apparatus comprising:

a base array memory, having inputs and outputs, for storing a record of a base array, said base array having a plurality of transistor-level devices;

a logic cell index memory, having inputs and outputs coupled to the base array memory, for storing transistor-level representations of physical implementations of a plurality of logic cells, each logic cell of said plurality comprising at least one of said transistor-level devices; and

an engine means, having inputs and outputs coupled to the base array memory and the logic cell index memory, for comparing said transistor-level devices in said base array with said at least one transistor-level device of each logic cell to test the placement of transistor-level representations of physical implementations of logic cells on the base array, and for generating a table of unique bit patterns specifying the legality of placing said transistor-level representations of physical implementations of logic cells at a plurality of locations on the base array, and for generating a location index map including for each of a plurality of locations on the base array a reference to the bit pattern in the legal location table that indicates the locations on the base array at which the transistor-level representations of physical implementations of logic cells can be placed.

23. The apparatus of claim 22, further comprising:

a basis memory, having inputs and outputs coupled to the base array memory, the logic cell index memory, and the engine means, for storing a record of a basis of the base array;

a floor plan memory, having inputs and outputs coupled to the base array memory, the logic cell index memory, the engine means, and the basis memory, for storing a floor plan of the base array; and

an array class means, having inputs and outputs coupled to the base array memory, the logic cell index memory, the engine means, the basis memory and the floor plan memory, for generating from the floor plan stored in the floor plan memory an array class and for storing at least one array class.

24. The apparatus of claim 22, further comprising a master cache means, having inputs and outputs coupled to the base array memory, the logic cell index memory and the engine means for manipulating the representations of physical implementations of logic cells stored in the logic cell index memory to generate at least one master cache from the representations of physical implementations of logic cells stored in the logic cell index memory, and for storing each master cache generated.

25. The apparatus of claim 22 further comprising:

a legal location table memory, having inputs and outputs coupled to the base array memory, the logic cell index memory, the engine means and the master cache means for storing at least one legal location table generated by the engine means; and

a legal location index map memory, having inputs and outputs coupled to the base array memory, the logic cell index memory, the engine means, the master cache means, and the legal location table memory, for storing at least one legal location index map generated by the engine means.

37. The apparatus of claim 22, wherein each transistor-level device is not automatically identified with one of said logic cells.

26. A method for testing placement of a plurality of representations of physical implementations of logic cells on a base array having a plurality of types of transistor-level devices, each of the transistor-level devices in a pre-determined location on the base array, each representation of a physical implementation of a logic cell including at least one transistor-level device, the method comprising the steps of:

identifying a group of transistor-level representations of physical implementations of logic cells having a type of transistor-level device in a pre-determined position in each transistor-level representation of a physical implementation of a logic cell in the identified group, including the steps of;

generating possible orientations of each transistor-level representation of a physical implementation of a logic cell;

separating a group of transistor-level representations of physical implementations of logic cells, from said possible orientations of each of said transistor-level representations of physical implementations of logic cells, wherein each representation of a physical implementation of a logic cell in this group has said type of transistor-level device in the pre-determined position; and

combining the transistor-level representations of physical implementations of logic cells within the group that are the same size and shape to produce a master cache;

building an array class of locations on the base array having said type of transistor-level device in the pre-determined position;

determining whether a selected transistor-level representation of a physical implementation of a logic cell of the identified group of representations of physical implementations of logic cells can be placed at a location in the array class including at least one of the following set of steps;

determining if the transistor-level devices that surround the location match the transistor-level devices of the selected transistor-level representation of a physical implementation of a logic cell;

determining if the transistor-level devices that surround the location are available for use by the selected transistor level representation of a physical implementation of a logic cell; and

determining if placing the selected transistor-level representation of a physical implementation of a logic cell at the location violates a design rule; and

constructing a bit pattern for each location in the array class, each bit pattern indicating the transistor-level representations of physical implementations of logic cells that can be placed at the location in the array class.

27. The method of claim 26, wherein the step of determining is performed for each transistor-level representation of a physical implementation of a logic cell in the identified group for locations in a basis of the base array;

and wherein the step of constructing is performed for each transistor-level representation of a physical implementation of a logic cell in the identified group for the locations in the basis of the base array.

28. The method of claim 27, further comprising the steps of:

eliminating duplicate bit patterns; and

constructing a table of the remaining, unique bit patterns.

29. The method of claim 28 further comprising the step of constructing a legal location index map of the array class including, for each location in the array class, a reference to a bit pattern in the table of unique bit patterns that identifies the transistor-level representations of physical implementations of logic cells that can be placed at that location.

30. The method of claim 29, further comprising the steps of:

determining a region along a boundary of the base array;

determining transistor-level representations of physical implementations of logic cells of the identified group that can be placed at the locations of the array class within the region;

adding bit patterns to the table of unique bit patterns for the locations of the array class within the region; and

altering the legal location index map for each location in the region to store the bit pattern that identifies the transistor-level representations of physical implementations of logic cells that can be placed at each respective location in the region.

31. The method of claim 30, wherein the step of determining the region along the boundary of the base array comprises the steps of:

selecting a first transistor-level representation of a physical implementation of a logic cell from the identified group of transistor-level representations of physical implementations of logic cells that is the largest transistor-level representation of a physical implementation of a logic cell in a vertical dimension;

determining a size of the first transistor-level representation of a physical implementation of a logic cell in the vertical dimension in terms of transistor-level devices;

subtracting one transistor-level device from the size of the first transistor-level representation of a physical implementation of a logic cell in the vertical dimension;

identifying rows of locations along an upper boundary of the base array wherein the number of rows is equal to the result of the subtracting step;

selecting a second transistor-level representation of a physical implementation of a logic cell from the group of transistor-level representations of physical implementations of logic cells that is the largest transistor-level representation of a physical implementation of a logic cell in a horizontal dimension;

determining the size in the horizontal dimension of the second transistor-level representation of a physical implementation of a logic cell in terms of transistor-level devices;

subtracting one transistor-level device from the size of the second transistor-level representation of a physical implementation of a logic cell in the horizontal dimension; and

identifying the columns of locations along a right boundary of the base array wherein the number of columns is equal to the result of the second subtracting step.

32. The method of claim 31, further comprising the steps of:

determining a region surrounding and occupied by a pre-existing structure on the base array;

determining the transistor-level representations of physical implementations of logic cells of the identified group that can be placed at the locations of the array class within the region;

adding bit patterns to the table, the bit patterns identifying the transistor-level representations of physical implementations of logic cells that can be placed at each location in the region; and

altering the map for each location in the region with the bit patterns that specify the transistor-level representations of physical implementations of logic cells that can be placed at the respective location in the region.

33. The method of claim 32, wherein the step of determining a region surrounding a pre-existing structure on the base array comprises the steps of:

identifying locations of the base array over the pre-existing structure;

selecting a first transistor-level representation of a physical implementation of a logic cell from the group of transistor-level representations of physical implementations of logic cells that is the largest transistor-level representation of a physical implementation of a logic cell in a vertical dimension;

determining the size in the vertical dimension of the first transistor-level representation of a physical implementation of a logic cell in terms of transistor-level devices;

first reducing the size of the first transistor-level representation of a physical implementation of a logic cell by one transistor-level device;

identifying rows of locations above and below the pre-existing structure on the base array wherein the number of rows is equal to the result of first reducing step in the vertical dimension;

selecting a second transistor-level representation of a physical implementation of a logic cell from the group of transistor-level representations of physical implementations of logic cells that is the largest transistor-level representation of a physical implementation of a logic cell in a horizontal dimension;

determining a horizontal size of the second transistor-level representation of a physical implementation of a logic cell in terms of transistor-level devices;

second reducing the horizontal size of the second transistor-level representation of a physical implementation of a logic cell by one; and

identifying the columns of locations along left and right sides of the pre-existing structure on the base array wherein the number of columns is equal to the second reducing step in the horizontal dimension.

34. The method of claim 26, wherein each transistor-level device is not automatically identified with one of said logic cells.