Non-volatile semiconductor memory device capable of high speed programming/erasure

• US 5,818,761 A
• Filed: 07/18/1997
• Issued: 10/06/1998
• Est. Priority Date: 09/10/1996
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Takada, Hiroshi, Hayashi, Kiyoshi, Onakado, Takahiro
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US08/897,101
• Time in Patent Office: 445 Days
• Field of Search: 365/185.18, 365/185.11, 365/185.13, 365/185.24, 365/189.09
• US Class Current: 365/185.18
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/3468 Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
• CPC Class Codes: G11C 16/3486 Circuits or methods to prevent overprogramming of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming

Abstract

To a column line to which a selected memory cell is connected, a write bias voltage is supplied through a selection gate transistor having different channel conductivity type than the memory cell transistor. Current drivability of the selection gate transistor is adapted to be larger than a leak current of the memory cell and to supply a current smaller than the channel current when a channel is formed in one aspect. When a verifying voltage is applied to the selected word line, a large channel current flows when a channel is formed, potential of a subbit line is changed accordingly, and programming is suppressed. In another aspect, the selection gate transistor serves as a constant current source to make the programming speed of the memory cells constant. Thus distribution of threshold values after programming can be made narrow.

Claims

1. A non-volatile semiconductor memory device comprising:

a plurality of memory cells arranged in rows and columns and each storing information, each said memory cells including a stacked gate transistor having a floating gate for accumulating charges and a control gate formed on said floating gate with an insulating film interposed between said floating gate and said control gate;

a plurality of column lines corresponding to said columns, each of said column lines connecting a prescribed number of memory cells of a corresponding column;

a plurality of row lines corresponding to said rows, each of said row lines connecting the control gates of the memory cells of a corresponding row;

a bias voltage transmitting circuit configured to operate in a special operation mode for reducing an absolute value of a threshold voltage of a selected memory cell of said plurality of memory cells, to transmit a prescribed bias voltage to a column line of said column lines connected to said selected memory cell, said bias voltage transmitting circuit having a smaller current supplying capability than a current drivability of said selected memory cell when the threshold voltage of said selected memory cell is lower than or equal to a prescribed absolute value in said special operation mode; and

a row selecting circuit for applying a prescribed potential to a row line of said plurality of row lines connected to said selected memory cell.

2. The non-volatile semiconductor memory device according to claim 1, wherein said bias voltage transmitting circuit includes:

a plurality of selection gate transistors corresponding to said plurality of column lines disposed in a substrate region formed in a region separate from a semiconductor substrate region having said plurality of memory cells formed thereon, for transmitting said prescribed bias voltage to a corresponding column line when selected; and

a column selecting circuit for applying mutually different prescribed voltage to a control electrode and the substrate region of a selection gate transistor corresponding to the column line connected to said selected memory cell to select said column selection gate transistor, wherein an absolute value of difference between the voltage at the control electrode of the selection gate transistor corresponding to said selected column line and the bias voltage is larger than an absolute value of the difference between said bias voltage and the voltage of said substrate region.

3. The non-volatile semiconductor memory device according to claim 2, wherein:

said stacked gate transistor forms a channel region of a first validity type when conducted;

said column selecting circuit includes means for applying a voltage, having a same polarity as and a smaller absolute value than said bias voltage, to the control electrode of the selection gate transistor corresponding to said selected column line, and applying a voltage having substantially the same magnitude as said bias voltage to the substrate region of the selection gate transistor corresponding to said selected column line; and

said selection gate transistor includes an insulated gate type field effect transistor forming a channel region of a second conductivity type when conducted.

4. The non-volatile semiconductor memory device according to claim 1, wherein

all the memory cells arranged on a column are connected to a corresponding column line.

5. The non-volatile semiconductor memory device according to claim 1, wherein each of the columns of said memory cells is divided into a plurality of groups each including a prescribed number of memory cells, each of said column lines is arranged corresponding to one of said plurality of groups, and each of said selection gate transistors electrically connects a main column line arranged common with the plurality of groups of a corresponding column to a corresponding column line when selected.

6. The non-volatile semiconductor memory device according to claim 1, wherein said bias voltage transmitting circuit includes:

a bias writing gate formed of an insulated gate type field effect transistor for transmitting said prescribed bias voltage, said bias writing gate being provided common to respective columns;

means for applying a voltage smaller in absolute value than said prescribed bias voltage and a voltage of an approximately identical magnitude with said bias voltage to a control electrode and a substrate region of said bias writing gate, respectively; and

a plurality of column selection gates, corresponding to respective ones of said columns, for transmitting the bias voltage from said bias write gate to the corresponding column lines, said plurality of column selection gates being rendered conductive in response to a column selection signal.

7. The non-volatile semiconductor memory device according to claim 6, wherein:

the stacked gate transistor of each of said memory cells forms a channel of a first conductivity type when conducted;

each of the column selection gates includes an insulated gate type field effect transistor forming a channel of the first conductivity type when conducted; and

said bias writing gate includes an insulated gate type field effect transistor forming a channel of a second conductivity type when conducted.

8. The non-volatile semiconductor memory device according to claim 1, wherein said row selecting circuit includes means for repeatedly and alternately applying voltage of mutually different polarities having a prescribed time width to the selected row line.

9. The non-volatile semiconductor memory device according to claim 8, wherein:

one of said voltages of mutually different polarities is a voltage for driving the selected row line to a selected state in said special operation mode; and

said non-volatile semiconductor memory device further includes means for adjusting at least one of a time width and a voltage level of another one of said voltages having mutually different polarities.

10. The non-volatile semiconductor memory device according to claim 1, further comprising

means for applying a second bias voltage to a conduction node different from a conduction node connected to the column line of the stacked gate transistor of the selected memory cell in said special operation mode.

11. The non-volatile semiconductor memory device according to claim 8, further comprising

means for applying a second bias voltage to a first conduction node of the stacked gate transistor of the selected memory cell during the application of the voltages of mutually different polarities, said first conduction node being different from a second conduction node connected to the column line of the stacked gate transistor of said selected memory cell.

12. The non-volatile semiconductor memory device according to claim 1, wherein said bias voltage transmitting circuit includes a transistor operating in a linear region to transmit said prescribed bias voltage.

13. The non-volatile semiconductor memory device according to claim 1, wherein said voltage transmitting circuit includes:

a plurality of selection gate transistors corresponding to the respective column lines said selection gate transistors being disposed in a substrate region formed in a region separate from a semiconductor substrate region having said plurality of memory cells formed thereon, for transmitting said prescribed bias voltage to a corresponding column line when selected;

column selecting circuitry for applying mutually different prescribed voltage to a control electrode and the substrate region of a selected selection gate transistor provided corresponding to the column line connected to said selected memory cell; and

an absolute value of a difference between the voltage at the control electrode of the selection gate transistor corresponding to the selected column line and the bias voltage is made larger than an absolute value of a difference between said bias voltage and the voltage of a control electrode of a selection gate transistor provided for a non-selected column line having no selected memory cell connected thereto.

14. A non-volatile semiconductor memory device, comprising:

a plurality of memory cells arranged in rows and columns, each storing information, each said memory cells including a stacked gate transistor having a floating gate for accumulating charges and a control gate formed on said floating gate with an insulating film interposed between said floating gate and said control gate;

a plurality of column lines corresponding to said columns, each of said column lines connecting a prescribed number of memory cells of a corresponding column;

a plurality of row lines corresponding to said rows, each of said row lines connecting a prescribed number of memory cells of the corresponding column;

a bias voltage transmitting circuit configured to operate in a special operation mode for reducing an absolute value of a threshold voltage of a selected memory cell, to transmit a prescribed bias voltage to selected column lines connecting the selected memory cell, said bias voltage transmitting circuit including means for supplying a constant current to said selected column line; and

a row driving circuit for applying a prescribed voltage to a selected row line connecting said selected memory cell.

15. The non-volatile semiconductor memory device according to claim 14, wherein:

said stacked gate transistor forms a channel of a first conductivity type when conducted;

said columns are divided into a plurality of groups, each group including a plurality of memory cells;

each column line is arranged corresponding to each group; and

said bias voltage transmitting circuit includes a plurality of selection gates, corresponding to said plurality of column lines, each formed of an insulated gate type field effect transistor forming a channel of a second conductivity type and operating in a saturation region to connect a corresponding main column line among main column lines arranged corresponding to respective columns when conducted.

16. The non-volatile semiconductor memory device according to claim 14, wherein:

said stacked gate transistor forms a channel of a first conductivity type when conducted, and all the memory cells of each said columns are connected to each respective column line; and

said bias voltage transmitting means includes;

a write gate transistor provided common to said columns and formed of an insulated gate type field effect transistor forming a channel of a second conductivity type when conducted, and

a plurality of column selection gates corresponding said column lines, each column selection gate forming a channel of the first conductivity type when conducted and transmitting a current and a bias voltage applied from said write gate transistor to a corresponding column line,

wherein said write gate transistor operates in a saturation region.

17. The non-volatile semiconductor memory device according to claim 14, wherein

said bias voltage transmitting means include an insulated gate type field effect transistor having a source for receiving said bias voltage, and a drain electrically coupled to the selected column line and operating in a saturation region.

18. The non-volatile semiconductor memory device according to claim 14, wherein said stacked gate transistor further includes a first conduction node coupled to receive said prescribed bias voltage and a second conduction node made open in said special operation node.

19. The non-volatile semiconductor memory device according to claim 14, further comprising an erase circuit, activated prior to said special operation mode, for selecting a predetermined number of memory cells including said selected memory cell and applying voltages to the stacked gate transistors of the predetermined number of memory cells thereby increasing the absolute value of a threshold voltage of the stacked gate transistors.

20. The non-volatile semiconductor memory device according to claim 19, wherein said bias voltage transmitting circuit includes means, activated prior to said special operation mode and subsequent to activation of said erase circuit, for applying a second bias voltage to said selected memory cell with a current driving capability smaller than that of the selected memory cell implemented when the threshold voltage of the selected memory cell reaches a predetermined value, and means for repeatedly and alternately applying a control voltage of different polarities and of predetermined time widths to a row line connecting the selected memory cell.