Drain voltage pump circuit for nonvolatile memory device

• US 5,818,766 A
• Filed: 03/05/1997
• Issued: 10/06/1998
• Est. Priority Date: 03/05/1997
• Status: Expired due to Term

• Current Assignee: Integrated Silicon Solution Incorporated (Uphill Investment Co.)
• Original Assignee: Integrated Silicon Solution Incorporated (Uphill Investment Co.)
• Inventors: Song, Paul Jei-Zen
• Primary Examiner(s): Dinh, Son T.
• Application Number:
  US08/811,946
• Time in Patent Office: 580 Days
• Field of Search: 365/189.11, 365/189.09, 365/226, 327/536, 327/548, 327/534, 327/535, 327/537
• US Class Current: 365/189.11
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence

Abstract

A program drain voltage pump is provided that employs multiple pumping sections that are adaptively controlled to provide a pumped drain voltage (VD) that rises smoothly and rapidly to an optimum VD level for programming EPROM or flash memory cells and maintains VD at the optimum level with minimal ripple. The pumping sections are configured to pump a common VD node that is coupled to the drains of the EPROM or flash memory cells. Each pumping section is driven by a clock signal whose pulses are out of phase with the clock signals driving the other pumping sections. All of the clock signals have roughly the same frequency. Due to the staggered clocks, each pump is activated during a different respective time period, which smooths out VD. Additionally, to provide an even faster and smoother pumped VD than with multiphase clocking alone, an embedded controller is provided that adaptively adjusts the frequency and slew rate of the various clock pulses throughout the pumping operation, which alters the amount by which VD is raised for a given clock pulse.

Claims

1. A drain voltage pump circuit comprising:

a ring oscillator circuit that provides at least three overlapping clock signals, each having a voltage profile and frequency controlled by the ring oscillator;

a plurality of pump sections, each of which is configured to pump a drain voltage (VD) node in response to a respective one of the clock signals;

the ring oscillator circuit individually controlling the frequency and the voltage profile of the clock signals so that the voltage at the VD node is pumped during an initial pumping interval from a VCC level to a target VD level and maintained throughout a programming cycle within a preset ripple range of the target VD level.

2. The drain voltage pump of claim 1, wherein, during a pumping operation, only the frequency of the clock signals is adjusted by the ring oscillator circuit.

3. The drain voltage pump of claim 1, wherein, during a pumping operation, only the voltage profile of the clock signals is adjusted by the ring oscillator circuit.

4. The drain voltage pump of claim 1, wherein, during a pumping operation, the frequency and voltage profile of the clock signals are adjusted simultaneously by the ring oscillator circuit.

5. The drain voltage pump of claim 1, wherein each of the pump sections comprises:

two native-mode transistors, wherein the gate of a first one of the native mode transistors is coupled to a program signal, the drain of the first transistor is coupled to a VCC node, the source of the first transistor is coupled to interconnected drain and gate of a second one of the transistors and the source of the second transistor is coupled to a drain voltage (VD) node; and

a capacitor, one terminal of which is coupled to the source of the first transistor and the interconnected drain and gate of the second transistor and a second terminal of which is coupled to a respective one of the clock signals.

6. The drain voltage pump of claim 1, wherein the capacitor comprises a native mode, MOS capacitor.

7. The drain voltage pump of claim 1, wherein the ring oscillator circuit comprises:

a plurality of oscillator sections, each of which generates one of the respective clock signals and includes;

an oscillator subsystem with a ring output coupled to a ring input of a subsequent oscillator subsystem and a ring input coupled to the ring output of a previous oscillator subsystem, the oscillator subsystem generating on its ring output signal pulses at a desired frequency determined by a control signal; and

an output circuit coupled to the ring output that, in response to each of the signal pulses, generates a clock pulse of the respective clock signal with a desired slew rate determined by the control signal;

a comparator that compares the voltage at the VD node (VD) to a target VD level (VD_target) and sets the control signal in accordance with the outcome of the comparison;

such that, when the control signal indicates a large difference between the VD and the VD_target, the oscillator subsystem increases the desired frequency and the output circuit increases the desired slew rate so that pumping action is increased; and

when the control signal indicates a small difference between the VD and the VD_target, the oscillator subsystem decreases the desired frequency and the output circuit decreases the desired slew rate so that pumping action is decreased.

8. The drain voltage pump of claim 7, wherein the clock signals comprise three overlapping clock signals and the plurality of oscillator subsections comprises three oscillator subsections.

9. The drain voltage pump of claim 7, wherein the comparator comprises:

a comparator circuit with inverting and non-inverting inputs, the non-inverting input being connected to a stable reference voltage and the inverting input being connected to a first voltage to be compared to the reference voltage; and

a voltage divider with one end connected to the VD node, the other end connected to a ground node and an output node that provides the first voltage, the voltage divider being configured so that the first voltage is close to the reference voltage when the VD is close to the VD_target ;

the comparator being configured to output the control signal so that the magnitude of the control signal is directly related to the difference between the VD and the VD_target.

10. The drain voltage pump of claim 9, wherein the reference voltage is determined by a bandgap reference voltage.

11. The drain voltage pump of claim 10, wherein the bandgap reference is approximately 1.28 V.

12. The drain voltage pump of claim 11, wherein the VD_target is between 5.5 volts and 6.0 volts.

13. The drain voltage pump of claim 9, wherein the voltage divider comprises:

two resistors R1 and R2 whose values are determined in accordance with;

##EQU2## where V_ref represents the voltage reference and R1 and R2 respectively represent the resistances of the resistors R1 and R2.

14. The drain voltage pump of claim 7, wherein the output circuit comprises:

a second inverter having an input driven by a periodic signal at the desired frequency, an output that provides a respective one of the clock signals and a pull-up input that is connected to the control signal, the inverter adjusting the slew rate of the corresponding clock signal in accordance with the magnitude of the control signal.

15. The drain voltage pump of claim 14, wherein the inverter is configured to adjust the slew rate of the respective clock signal by providing a faster slew rate when the control signal is large and with a slower slew rate when the control signal is small.

16. The drain voltage pump of claim 15, wherein the second inverter comprises:

first and second n-channel, native-mode transistors;

first and second p-channel transistors;

an inverting circuit; and

a capacitor;

the first n-channel transistor having a gate coupled to a second reference voltage, a source coupled to a ground node and a drain coupled to the drain of the first p-channel transistor;

the first p-channel transistor having interconnected gate and drain terminals and a source coupled to the VCC node;

the second n-channel transistor having a gate coupled to the control signal, a source coupled to the ground node and a drain coupled to the gate and drain of the first p-channel transistor;

the second p-channel transistor being the same size as the first p-channel transistor and having a gate coupled to the gate of the first p-channel transistor, a source coupled to the VCC node and a drain coupled to a pull-up that determines how much current is supplied to the inverting circuit, the supplied current mirroring the current drawn by the first p-channel transistor;

the inverter having a second input that is coupled to the output of the first inverter and a second output that provides the corresponding clock signal;

the capacitor being connected between the ground node and the second output, such that the capacitor determines the slew rate of the corresponding clock signal in direct correlation with the level of the supplied current, the level of the supplied current being large when the control signal is large and small when the control signal is small.

17. The drain voltage pump of claim 16, wherein the second reference voltage is determined by a bandgap reference voltage.

18. The drain voltage pump of claim 17, wherein the bandgap reference is approximately 1.28V.