Redundancy circuit for programmable integrated circuits

• US 5,818,778 A
• Filed: 03/26/1997
• Issued: 10/06/1998
• Est. Priority Date: 06/06/1995
• Status: Expired due to Term

• Current Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Lui, Sik K., Pilling, David J., Chu, Raymond M.
• Primary Examiner(s): YOO, DO H
• Application Number:
  US08/824,591
• Time in Patent Office: 559 Days
• Field of Search: 365/225.7, 365/189.09, 365/96, 365/189.01
• US Class Current: 365/225.7
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 29/781 combined in a redundant decoder
• CPC Class Codes: G11C 29/785 with redundancy programming schemes
• CPC Class Codes: Y10S 257/919 Elements of similar construction connected in series or parallel to average out manufacturing variations in characteristics

Abstract

An antifuse redundancy circuit operates with transparency to external circuitry and users. In one embodiment, an antifuse redundancy circuit incorporates two antifuses rather than one. The circuit is arranged so that both antifuses may be simultaneously programmed and read. If a single antifuse is programmed without programming the other antifuse, the antifuse redundancy circuit will register a programmed antifuse. Additionally, if a single programmed antifuse is unintentionally deprogrammed after both antifuses in the redundancy circuit have been programmed, the antifuse redundancy circuit will continue to register a programmed antifuse. The result is both an increase in manufacturing yield and an increase in the reliability of integrated circuits utilizing antifuses.

Claims

1. A circuit comprising:

an antifuse cell comprising;

a first antifuse;

a second antifuse;

an output node to conduct a state of the antifuse cell, wherein the antifuse cell has only a single state during any period of time;

a read node;

a program circuit for coupling a programming voltage across the first and second antifuses; and

a read circuit for coupling a read voltage across the first and second antifuses and, in response to a read signal on the read node which selects the antifuse cell, for providing a state of the antifuse cell to the output node which corresponds to a programmed state of the first and second antifuses when both of the first and second antifuses are programmed and corresponds to the programmed state of one of the first and second antifuses if only one of the first and second antifuses is programmed;

wherein when at least one of the first and second antifuses is programmed, the antifuse cell is in a programmed state, the programmed state being the same when one of the first and second antifuses is programmed and when both antifuses are programmed to provide redundancy to the antifuse cell.

2. The circuit as in claim 1 wherein the program circuit includes:

a program terminal;

a voltage bias circuit having a control terminal coupled to the program terminal and a voltage node;

a first PMOS transistor having a source coupled to a first voltage node, a drain coupled to a terminal of the first antifuse, and a gate coupled to the program terminal; and

a first NMOS transistor having a source coupled to a second voltage node, a drain coupled to the second antifuse, and a gate coupled to the voltage node of the voltage bias circuit.

3. The circuit as in claim 1 wherein the circuit is an integrated circuit selected from the group consisting of a microprocessor, a memory, and a field programmable gate array.

4. A circuit comprising:

a first voltage node;

a second voltage node;

a first antifuse having a first terminal coupled to the first voltage node and having a second terminal;

a second antifuse having a first terminal coupled to the second voltage node and having a second terminal;

a first switch having current terminals coupled between the first antifuse second terminal and the second voltage node and having a control terminal;

a second switch having current terminals coupled between the second antifuse second terminal and the first voltage node and having a control terminal;

a read output node coupled to the first antifuse second terminal and the second antifuse second terminal;

an output terminal;

a READ signal terminal;

a pass switch having current terminals coupled between the read output node and the output terminal and a control terminal coupled to the READ terminal;

and

a PROGRAM signal terminal coupled to the first switch control terminal and to the second switch control terminal, wherein the first and second switches conduct when the PROGRAM signal terminal has a program signal.

5. The circuit of claim 4 further comprising:

a third switch having a control terminal coupled to the second antifuse second terminal and having current terminals coupled between the read output node and the second voltage node; and

a fourth switch having a control terminal coupled to the first antifuse second terminal and having current terminals coupled between the third switch control terminal and the second voltage node.

6. The circuit of claim 5 wherein the second switch and the pass switch are PMOS field effect transistors and the first, third and fourth switches are NMOS field effect transistors.

7. The circuit of claim 4 wherein the first voltage node is coupled to a +5V voltage reference and the second voltage node is coupled to a -5V voltage reference.

8. The circuit of claim 4 further comprising:

a voltage bias circuit having a control terminal coupled to the PROGRAM terminal, a voltage node coupled to the first switch control terminal, a first current terminal coupled to the first voltage node, and a second current terminal coupled to the second voltage node.

9. The circuit of claim 8 wherein the voltage bias circuit includes:

a third switch having current terminals coupled between the first voltage node and the voltage node of the voltage bias circuit and a control terminal coupled to the PROGRAM terminal;

a fourth switch having a first current terminal and a control terminal coupled to the voltage node of the voltage bias circuit, and a second current terminal; and

a fifth switch having a first current terminal and a control terminal coupled to the fourth switch second current terminal and a second current terminal coupled to the second voltage node.

10. The circuit of claim 9 further comprising:

a third voltage node; and

a discharge circuit coupled between the voltage bias circuit voltage node and the third voltage node.

11. A circuit having an antifuse cell comprising:

a first antifuse having first and second terminals;

a second antifuse having first and second terminals;

an output node to conduct a state of the circuit wherein the circuit has only a single state during any period of time;

a read node to conduct a read signal that selects both the first and second antifuses;

means for applying a programming voltage across the first and second terminals of both the first and second antifuses to program one or both of the first and second antifuses; and

means for determining the state of the circuit at the output node if the read node conducts the read signal,

wherein the circuit has the same programmed state when one of the first and second antifuses is programmed and when both of the first and second antifuses are programmed, and a failure of one of the first and second antifuses to program has no effect on the circuit programmed state.

12. A method of programming and reading antifuses in a circuit, the method comprising the steps of:

applying a programming voltage approximately simultaneously across a first antifuse and a second antifuse of an antifuse cell to program at least one of the first and second antifuses, the antifuse cell having only a single state during any period in time and the state of the antifuse cell being the same upon one of the first and second antifuses being programmed and upon both of the first and second antifuses being programmed;

applying a read voltage approximately simultaneously across the first and second antifuses in response to a read signal present on a READ node which selects both the first and second antifuses;

coupling a first potential to a READ OUTPUT node when the first and second antifuses are not programmed; and

coupling a second potential to the READ OUTPUT node when only one of the first and second antifuses is programmed and when both the first and second antifuses are programmed so that the first and second antifuses provide redundancy to the antifuse cell.

13. The method as in claim 12 wherein the step of applying a read voltage comprises:

applying a read signal to a switch to couple the first and second antifuses to the READ OUTPUT node.

14. The method as in claim 13 further comprising the step of:

applying the read signal to a pass transistor to couple the READ OUTPUT node to an OUTPUT node.

15. The method as in claim 12 wherein the programming voltage applying step comprises:

applying a program voltage signal to a plurality of field effect transistors so that the programming voltage is applied across the first and second antifuses.

16. A method of programming and reading antifuses in a circuit having an antifuse cell, the method comprising the steps of:

programming a first antifuse and a second antifuse of the antifuse cell approximately simultaneously to place the antifuse cell of the circuit in a programmed state; and

reading a state of the antifuse cell of the circuit in response to a read signal on a READ node which selects the first antifuse and the second antifuse, wherein the antifuse cell conveys only a single state to the circuit during a period of time, and the antifuse cell has the same programmed state when one of the first and second antifuses is programmed and when both of the first and second antifuses are programmed.

17. The method as in claim 16 wherein the programming step comprises the steps of:

applying a programming voltage across the first antifuse; and

applying a programming voltage across the second antifuse;

wherein at least one of the first and second antifuses is programmed.

18. The method as in claim 16 wherein the reading step comprises the steps of:

applying a reading voltage across the first antifuse;

applying a reading voltage across the second antifuse; and

coupling a potential corresponding to the programmed state to a read output node when at least one of the antifuses is programmed.

19. A method of improving the yield and reliability of a circuit having an antifuse cell which includes a first antifuse, the method comprising the steps of:

adding a second antifuse to the antifuse cell; and

programming the first and second antifuses to place the antifuse cell in a programmed state;

selecting both the first and second antifuses with a read signal;

providing a single programmed state of the antifuse cell to an output node in response to the read signal, wherein the single programmed state of the antifuse cell is based on the states of the first and second antifuses;

wherein the second antifuse has been added to the antifuse cell in such a manner as to cause the antifuse cell to adopt the same programmed state when the first antifuse alone is programmed, when the second antifuse alone is programmed, and when both the first and second antifuses are programmed.