Circuit technique for logic integrated DRAM with SIMD architecture and a method for controlling low-power, high-speed and highly reliable operation

• US 5,818,788 A
• Filed: 05/30/1997
• Issued: 10/06/1998
• Est. Priority Date: 05/30/1997
• Status: Expired due to Term

• Current Assignee: Massachusetts Institute of Technology, NEC Corporation
• Original Assignee: Massachusetts Institute of Technology, NEC Corporation
• Inventors: Kimura, Tohru, Sodini, Charles G.
• Primary Examiner(s): LE, VU ANH
• Application Number:
  US08/865,968
• Time in Patent Office: 494 Days
• Field of Search: 365/230.03, 365/52, 365/233
• US Class Current: 365/230.03
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device

Abstract

In a logic integrated DRAM LSI with SIMD architecture, a intentional clock skew is introduced for both between DRAM blocks and between logic blocks due to reduce the magnitude of peak current, operation frequency and number of I/O are defined for both DRAM blocks (frequency f_M, I/O number m) and logic blocks (frequency f_N, I/O number n) to keep the relation of

f.sub.M ×m=f.sub.N ×n,

address out of order scheme is introduced to achieve a high-speed and low-power DRAM access.

Claims

1. A logic integrated DRAM LSI with SIMD architecture comprising:

a plurality of memory blocks, plurality of logic blocks, a plurality of data signal lines connected for transmitting and receiving data between associated ones of said memory blocks and said logic blocks, a plurality of control blocks operative to control said memory and logic blocks, a plurality of clock generation blocks, a plurality of control signal lines connected to said memory blocks and said logic blocks, a plurality of signal lines for outputting and inputting external signals, said plurality of logic blocks being driven according to a single-instruction-multiple-data-stream (SIMD) manner, said LSI further comprising;

means for driving each memory block at different timings and for driving each logic block at different timings, the timing difference comprising 1/ M×

f! for memory blocks and 1/ N×

f! for logic blocks, wherein the number of memory blocks is M, the number of logic block is N and the LSI operation frequency is f.

2. A logic integrated DRAM LSI with SIMD architecture in claim 1 wherein,

when the operation frequency for memory blocks is f_M, the operation frequency for logic block is f_N, the I/O number of each memory block is m and the I/O number of each logic block is n, these values satisfy the following relation,

3. A logic integrated DRAM LSI with SIMD architecture in claim 1 further comprising,

means for changing the order in which addresses issue in order to minimize the number of word address changes required for access to said memory blocks and retrieval of data therefrom, and for restoring said retrieved data to the original address order after memory access.

4. A logic integrated DRAM (LSI) with SIMD architecture in claim 1 wherein said means for driving comprises a phase locked loop having a plurality of taps, each connected to a respective logic block.

5. A logic integrated DRAM LSI with SIMD architecture in claim 4 wherein said phase lock loop comprises a voltage controlled oscillator.

6. A logic integrated DRAM LSI with SIMD architecture in claim 1 wherein said means for driving comprises a delayed locked loop.

7. A logic integrated DRAM LSI with SIMD architecture in claim 1 wherein said means for driving comprises a synchronous mirror delay circuit.

8. A method of accessing a logic integrated DRAM LSI with SIMD architecture, said LSI comprising a plurality of memory blocks, each memory block having connected thereto a corresponding logic block that is responsive to a clock signal for effecting access to said memory block, comprising;

generating a clock signal for effecting access to said plurality of memory blocks by said logic blocks;

delaying said clock signal; and

applying said delayed clock signal to said logic blocks at different timings.

9. The method of accessing a logic integrated DRAM LSI with SIMD architecture as set forth in claim 8 wherein said memory blocks and said logic blocks are driven at different timings and the timing difference comprising 1/ M×

f! for memory blocks and 1/ N×

f! for logic blocks, wherein the number of memory blocks is M, the number of logic block is N and the LSI operation frequency is f.

10. The method of accessing a logic integrated DRAM LSI with SIMD architecture as set forth in claim 8 wherein when the operation frequency for memory blocks is f_M, the operation frequency for logic block is f_N, the I/O number of each memory block is m and the I/O number of each logic block is n, these values satisfy the following relation,

11. The method of accessing a logic integrated DRAM LSI with SIMD architecture as set forth in claim 8, further comprising changing the order in which addresses issue in order to minimize the number of word address changes required for access to said memory blanks and retrieval of data therefrom, and restoring said retrieved data to the original address order after memory access.