Method of using a four-state simulator for testing integrated circuit designs having variable timing constraints

• US 5,819,072 A
• Filed: 06/27/1996
• Issued: 10/06/1998
• Est. Priority Date: 06/27/1996
• Status: Expired due to Term

• Current Assignee: Unisys Corporation
• Original Assignee: Unisys Corporation
• Inventors: Bushard, Louis B., Paul, Richard F., Criswell, Peter B., Fuller, Douglas A., Rezek, James E.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): Fiul, Dan
• Application Number:
  US08/671,432
• Time in Patent Office: 831 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 364/578, 395/500
• US Class Current: 716/104
• CPC Class Codes: G06F 30/3312 Timing analysis

Abstract

Method for performing critical path timing analysis on a circuit design having different timing constraints for multiple parallel paths. Method includes clearing the state of the circuit design, setting control lines in the circuit design to a selected set of control signals, and identifying blocking nets of the circuit design to be flagged for timing analysis by simulating the circuit design with the selected set of control signals as input signals. Identified blocking points are added to a list which identifies paths in the circuit design to be analyzed. All possible sets of control signals are processed. Timing analysis is then performed on the circuit design using the list as input data. A critical step is the identification of the blocking points. Blocking points are identified for each net input to a gate in the circuit design having an unknown value, and a known value on an output net from the gate for the selected set of control signals. Blocking points input to the timing analysis tool ensure that these nets are analyzed during critical path timing analysis, so all possible timing violations in the circuit design are detected.

Claims

1. In a system for performing timing analysis on circuit designs having different timing constraints for multiple parallel paths, a computer-implemented method comprising the steps of:

(a) clearing the state of the circuit design;

(b) setting control lines in the circuit design to a selected set of control signals;

(c) identifying blocking points of the circuit design to be flagged for timing analysis by simulating the circuit design with said selected set of control signals as input signals;

(d) adding said blocking points to a list, said list identifying paths in the circuit design to be analyzed and further indicating portions of the circuit design to be disregarded during timing analysis;

(e) repeating steps (a)-(d) for all possible sets of control signals; and

(f) performing timing analysis on the circuit design using said lists.

2. The computer-implemented method of claim 1, wherein the circuit designs each include nets and gates, each of said gates having input and output terminals, and wherein step (c) identifies each of said blocking points as being an input terminal of an associated gate, said input terminal receiving a net having an unknown logic level when said associated gate drives a net having a known logic level and when said selected set of control signals are selected for said control lines.

3. The computer-implemented method of claim 1, wherein step (f) performs timing analysis by executing a critical path algorithm.

4. A system for performing timing analysis on a circuit design of a circuit including nets and components, wherein predetermined ones of the components are state devices, the circuit further having control lines to control the transfer of data signals from ones of the state devices to others of the state devices, the circuit including paths, each path comprising nets and components that interconnect a driving one of the state devices and a receiving one of the state devices and whereby the driving one of the state devices can propagate a signal to the receiving one of the state devices, ones of the paths being parallel paths, wherein each of the parallel paths is associated with at least one other parallel path, the parallel paths which are associated each drive the same state device and have a different maximum allowable propagation delay from one another such that the paths which are associated have different timing constraints, the system for performing timing analysis on the circuit design, comprising:

storage means for storing identifiers of paths in a circuit design to be analyzed;

simulation means coupled to said storage means, said simulation means for associating a predetermined initial logical state with each net and each state device in said circuit design, for setting control lines in said circuit design to a selected logical state, for identifying blocking points of the circuit design to be flagged for timing analysis by simulating said circuit design with said selected set of control lines set to said selected logical state and utilized as input signals, and for storing said blocking points in said storage means; and

timing analysis means coupled to said storage means for performing timing analysis on the circuit design using said blocking points, whereby each of said blocking points indicates paths of the circuit to be temporarily disregarded during timing analysis.

5. The system of claim 4, wherein each of the components have an input terminal and an output terminal, wherein said simulation means further includes means for identifying each of said blocking points as an input terminal of a component that receives, during simulation, a signal having an unknown logical state, and wherein said component drives an output net having a known logical state.

6. The system of claim 4, wherein each of the nets and each of the state devices in the circuit design may at a given point in time be associated with any one of four predetermined logical states, and wherein said simulation means is capable of performing boolean simulation on the circuit design using the associated ones of said four predetermined logical states.

7. The system of claim 4, wherein said timing analysis means includes means for executing a critical path algorithm.

8. The system of claim 4, further including means for storing timing notes written by a test engineer, said timing notes being input to said simulation means and said timing analysis means to direct simulation and timing analysis processing.

9. The system of claim 4, further including means for reporting timing violations found in said circuit design by said timing analysis means.

10. In an electronic design automation system for performing timing analysis on integrated circuit designs having gates and nets, ones of the gates being state devices receiving a clock signal, ones of the nets being control lines for controlling the transfer of data signals from ones of the state devices to other ones of the state devices, the integrated circuit design further including paths including gates and nets, ones of the paths being parallel paths such that each of the parallel paths is associated with at least one other parallel path and the associated parallel paths each drives the same one of the state devices, and wherein ones of the associated parallel paths have different timing constraints, a computer-implemented method, comprising the steps of:

(a) writing timing notes to direct boolean simulation and timing analysis processing on an integrated circuit design;

(b) clearing the state of nets in said integrated circuit design;

(c) setting control lines in said integrated circuit design to a selected set of control signals;

(d) setting a timing delay constraint for paths selected by said selected set of control signals;

(e) creating a block list for storing identifiers of nets of said integrated circuit design to be flagged for timing analysis;

(f) identifying blocking points by simulating said integrated circuit design with said selected set of control signals as input signals, said blocking points identifying which paths of the integrated circuit design are not to be processed during timing analysis;

(g) recording the identification of said blocking points within said block list;

(h) repeating steps (b)-(g) for all possible sets of control signals;

(i) performing critical path timing analysis on said integrated circuit design, said block lists identifying which paths in the integrated circuit design are to be analyzed and which paths are to be temporarily ignored; and

(j) reporting any timing violations detected by step (i).

11. The computer-implemented method of claim 10, wherein said blocking points are identified for each net input to a gate in said integrated circuit design having an unknown value on an input net and a known value on an output net from said gate for said selected set of control signals.

12. A system for performing timing analysis on a representation of a circuit design including nets and further including parallel paths having different timing constraints, comprising:

identification means for identifying ones of the nets as control lines which control the transfer of data signals within the circuit design;

simulation means coupled to said identification means for receiving the identification of said control lines, said simulation means for initializing the representation of the circuit design to a predetermined initial state, for setting ones of said control lines to a predetermined logical state, and for performing boolean simulation to identify ones of the paths in the circuit design which do not affect the operation of the circuit design when said control lines are set to said predetermined logical state, said identified ones of the paths being designated as unselected paths; and

timing analysis means coupled to said storage means for receiving identities of said unselected paths, and for performing timing analysis on the representation of the circuit design without analyzing said unselected paths.

13. The system of claim 12 wherein said timing analysis means further includes means for performing critical path timing analysis.

14. The system of claim 12 wherein said simulation means further includes means to cause said boolean simulation to be automatically performed for all allowable logical states of said control lines.

15. In an electronic design automation system for performing timing analysis on a circuit design having combinational logic components, state devices, and nets, the circuit design further including paths which include those combinational logic components and nets which may provide a signal from an associated driving one of the state devices to an associated receiving one of the state devices, ones of the paths being parallel paths such that each of the parallel paths is associated with at least one other parallel path and the associated ones of the parallel paths each drive the same one of the state devices and have timing delay constraints which are different from each other, a computer-implemented method comprising the steps of:

(a) writing timing notes to indicate ones of the nets which are control signals;

(b) setting the state of nets and state devices in said circuit design to a predetermined initial state;

(c) setting selected ones of said control signals to a predetermined logical state;

(d) setting a timing delay constraint for paths selected by said selected ones of said control signals when said ones of said control signals are set to said predetermined logical state;

(e) performing boolean simulation to identify those paths of said circuit design which are not selected by said ones of said selected control signals when said selected ones of said control signals are set to said predetermined logical state;

(f) recording the identities of the paths identified in step (e) in a block list which is associated with said predetermined logical state of said selected ones of said control signals;

(g) repeating steps (b)-(f) for all possible logical states of said control signals;

(h) designating all paths in the circuit design as not being blocked paths;

(i) designating all paths recorded in a selected one of said block lists as blocked paths within the circuit design;

(j) performing timing analysis to locate timing violations existing in the circuit design, said critical path timing analysis temporarily disregarding said blocked paths; and

(k) repeating steps (h)-(j) for each of said block lists created in said steps (b)-(f).

16. The computer-implemented method of claim 15, wherein said step of performing timing analysis includes performing critical path timing analysis.

17. The computer-implemented method of claim 15, wherein said step (e) includes the steps of:

(e1) identifying combinational logic components driving nets with a known logical state;

(e2) determining if any of said identified combinational logic components identified in step (e1) have an input terminal having an unknown logical state and which is associated with a driven net with a known logical state; and

(e3) identifying paths driving said inputs terminals identified is said step (e2) as being paths which are not selected.