Random access memory assembly

• US 5,819,304 A
• Filed: 03/24/1997
• Issued: 10/06/1998
• Est. Priority Date: 01/29/1996
• Status: Expired due to Term

• Current Assignee: Aonix
• Original Assignee: Iowa State University Research Foundation Incorporated (Iowa State University)
• Inventors: Schmidt, William, Nilsen, Kelvin D.
• Primary Examiner(s): Chan, Eddie P.
• Assistant Examiner(s): Bragdon, R. G.
• Application Number:
  US08/823,464
• Time in Patent Office: 561 Days
• Field of Search: 711/5, 711/104-106, 711/211, 711/172
• US Class Current: 711/5
• CPC Class Codes: G06F 12/0253 Garbage collection, i.e. reclamation of unreferenced memory
• CPC Class Codes: G06F 12/0269 Incremental or concurrent garbage collection, e.g. in real-time systems G06F12/0261 takes precedence

Abstract

The invention is a random access memory assembly which is a key component of an object space manager which in turn is a key circuit in a garbage-collecting control unit for a computer system. An object space manager provides the means for deriving pointers to headers of objects from pointers to internal data of objects. The object space manager comprises an encoder that generates an object locator code for each memory cell in which an object is resident, a random access memory assembly for storing the object locator codes for all memory cells in which objects are resident, and an object locator which identifies the memory cell containing the header of an object by means of the object locator code for any memory cell occupied by the object.

Claims

1. A random access memory assembly (RAMA) comprising G random access memories (RAMs) identified by the integers from 1 to G, said RAMA having log₂ F address lines and G sets of data lines, log₂ F being an integer, one set of data lines being associated with each of said RAMs, said RAMA address lines being numbered from 1 to log₂ F in order of address bit significance, address line 1 corresponding to the most significant bit, the address lines for RAM H being address lines 1 to log₂ (F/N_H-1), H taking on every integer value from 1 to G, log₂ N_H being an integer less than or equal to log₂ F, N_G being equal to F, N₀ being equal to 1, the values of N_H being different for different values of H.

2. The random access memory assembly (RAMA) of claim 1 wherein RAM H has at least (log₂ N_H) data lines.

3. The random access memory assembly (RAMA) of claim 1 wherein RAM H has at least (log₂ (N_H /N_H-1,)) data lines.