Electric device, matrix device, electro-optical display device, and semiconductor memory having thin-film transistors

• US 5,821,559 A
• Filed: 03/30/1995
• Issued: 10/13/1998
• Est. Priority Date: 02/16/1991
• Status: Expired due to Term

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Takemura, Yasuhiko, Yamazaki, Shunpei
• Primary Examiner(s): BROWN, PETER T
• Application Number:
  US08/413,885
• Time in Patent Office: 1,293 Days
• Field of Search: 257/346, 257/347, 257/349, 257/352, 257/285-287, 257/55, 257/57, 257/63, 257/66, 257/67, 257/77, 257/368, 257/369, 257/378, 257/379, 359/54, 359/55, 359/59
• US Class Current: 257/57
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/136245 having complementary transistors
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3659 the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/8213 the substrate being a semiconductor, using SiC technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78651 Silicon transistors H01L29/78606 - H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78666 with normal-type structure, e.g. with top gate
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate

Abstract

A circuit adapted to dynamically activate an electro-optical display device is constructed from a thin-film gate-insulated semiconductor device. This device comprises PMOS TFTs producing only a small amount of leakage current. Besides the dynamic circuit, a CMOS circuit comprising both NMOS and PMOS thin-film transistors is constructed to drive the dynamic circuit.

Claims

1. A memory device comprising:

a substrate having an insulating surface;

a p-type thin film transistor provided over said substrate;

a driving circuit provided over said substrate for driving said p-type thin film transistor, said driving circuit comprising at least one pair of complementary thin film transistors,

wherein at least one of said p-type thin film transistor or said one pair of complementary thin film transistors comprises a semiconductor layer including source, drain and channel regions, a gate insulating film formed on said semiconductor layer and a gate electrode formed on said insulating film,

wherein said channel region has a higher crystallinity in an upper portion close to said gate electrode and a lower crystallinity in a lower portion distant from said gate electrode.

2. A memory device according to claim 1 wherein said upper portion of the channel region comprises crystalline silicon while said lower portion of the channel region comprises amorphous silicon.

3. A memory device according to claim 1 wherein said device is an active matrix device.

4. A memory device according to claim 1 wherein said device is a DRAM.

5. A memory device according to claim 1 wherein said upper portion has a single crystal structure.

6. A memory device comprising:

a substrate having an insulating surface;

a thin film transistor provided on said insulating surface, said transistor having at least a channel region, source and drain regions with said channel region therebetween, a gate insulating film formed on said channel region and a gate electrode formed on said gate insulating film; and

a capacitor connected to said drain region of the transistor on said insulating surface,

wherein said channel region comprises a first semiconductor layer in contact with said gate insulating film and a second semiconductor layer disposed between said first semiconductor layer and said insulating surface, said first semiconductor layer having a higher crystallinity than said second semiconductor layer.

7. A memory device according to claim 6 wherein said second semiconductor layer has an amorphous structure.

8. A memory device according to claim 6 wherein said thin film transistor is a p-channel type.

9. A memory device according to claim 6 wherein said first semiconductor layer comprises single crystal silicon.

10. A memory device comprising:

a substrate having an insulating surface;

a first thin film transistor provided over said substrate;

a capacitor connected to a drain of said thin film transistor; and

a driving circuit provided over said substrate for driving said thin film transistor, said driving circuit comprising second thin film transistors,

wherein at least one of first and second thin film transistors comprises a semiconductor layer including source, drain and channel regions, a gate insulating film formed on said semiconductor layer and a gate electrode formed on said gate insulating film,

wherein said channel region has a higher crystallinity in an upper portion close to said gate electrode and a lower crystallinity in a lower portion distant from said gate electrode.

11. A memory device according to claim 10 wherein said upper portion has a single crystal structure.

12. A memory device comprising:

a substrate having an insulating surface;

a first thin film transistor provided over said substrate;

a capacitor connected to a drain of said thin film transistor; and

a driving circuit provided over said substrate for driving said thin film transistor, said driving circuit comprising second thin film transistors,

wherein said first and second thin film transistors are formed through a common process and comprises a semiconductor layer including source, drain and channel regions, a gate insulating film formed on said semiconductor layer and a gate electrode formed on said gate insulating film,

wherein said channel region has a higher crystallinity in an upper portion close to said gate electrode and a lower crystallinity in a lower portion distant from said gate electrode.

13. A memory device according to claim 12 wherein said upper portion has a single crystal structure.

14. A memory device comprising:

a substrate having an insulting surface;

a plurality of bit lines formed over said substrate;

a plurality of word lines formed over said substrate;

a plurality of memory regions in the form of matrix formed at each intersection of said bit lines and said word lines;

a plurality of thin film transistors provided in said memory regions, each of said thin film transistors comprising;

a semiconductor layer;

a channel region formed in said semiconductor layer;

source and drain regions formed in said semiconductor layer with said channel region therebetween;

a gate insulating film on said semiconductor layer; and

a gate electrode formed over said channel region with said gate insulating film therebetween,

a plurality of capacitors provided in said memory regions; and

a driver circuit operatively connected to said plurality of thin film transistors through said bit lines and said word lines, said driver circuit comprising thin film transistors,

wherein said channel region has a higher crystallinity in an upper portion close to said gate electrode and a lower crystallinity in a lower portion distant from said gate electrode.

15. A memory device comprising:

a plurality of memory elements formed over a substrate, each element comprising a thin film insulated gate field effect transistor having a crystalline channel region;

a driver circuit for driving said memory elements,

wherein said crystalline channel region comprises single crystal silicon.

16. A memory device according to claim 15 wherein said thin film insulated gate field effect transistor is a p-channel transistor.

17. A memory device comprising:

a plurality of memory elements formed over a substrate;

a driver circuit for driving said memory elements, said driver circuit comprising thin film insulated gate field effect transistors formed over said substrate,

wherein each channel region of said transistors comprises single crystal silicon.

18. A memory device according to claim 17 wherein said transistors constitute an inverter circuit.

19. A memory device according to claim 17 wherein said transistors constitute a CMOS circuit.