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TFT with self-align offset gate

  • US 5,821,564 A
  • Filed: 05/23/1997
  • Issued: 10/13/1998
  • Est. Priority Date: 05/23/1997
  • Status: Expired due to Term
First Claim
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1. An offset structure of PMOS thin film transistor, wherein said PMOS thin film transistor comprises:

  • a gate region having a disconnected portion;

    a source region being above said gate region;

    a drain region being above said gate region;

    a first channel region being above said gate region and adjacent to said source region and substantially aligned with said gate;

    a second channel region being above said gate region and adjacent to said drain region and substantially aligned with said gate;

    an offset region disposed between said first channel region and said second channel region and being in said gate disconnection portion;

    and wherein said offset region has a trench-like profile.

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