TFT with self-align offset gate

• US 5,821,564 A
• Filed: 05/23/1997
• Issued: 10/13/1998
• Est. Priority Date: 05/23/1997
• Status: Expired due to Term

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: Mosel Vitelic Incorporated
• Inventors: Wu, Hsiao-Chia, Kao, Jung-Cheng, Chang, Thomas
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): NGUYEN, CUONG QUANG
• Application Number:
  US08/862,318
• Time in Patent Office: 508 Days
• Field of Search: 257/66, 257/350, 257/351, 257/69, 257/903, 257/329, 257/347, 257/372, 257/401, 438/151, 438/159, 438/166, 438/286, 438/150
• US Class Current: 257/66
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78645 with multiple gate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: Y10S 257/903 FET configuration adapted for use as static memory cell

Abstract

A PMOS thin film transistor (TFT) with self-align offset region for SRAM application is described. A source and a drain regions are above the gate region. A channel region is formed offset from the gate. An offset region is formed in the channel region having a length of 0.3 to 0.4 μm. The key point of the present invention is the novel offset design of PMOS-TFT as load elements in an SRAM cell. Unlike the conventional offset design which is outside the gate, the offset region of the present invention is a disconnection region inside the gate which can be easily formed by so called self-align technique. Since the gate has a disconnected portion in the offset region, the trench-like profile of the offset region makes the load resistance in the offset region much higher to effectively reduce the leakage current.

Claims

1. An offset structure of PMOS thin film transistor, wherein said PMOS thin film transistor comprises:

a gate region having a disconnected portion;

a source region being above said gate region;

a drain region being above said gate region;

a first channel region being above said gate region and adjacent to said source region and substantially aligned with said gate;

a second channel region being above said gate region and adjacent to said drain region and substantially aligned with said gate;

an offset region disposed between said first channel region and said second channel region and being in said gate disconnection portion;

and wherein said offset region has a trench-like profile.

2. The structure of claim 1, wherein said self-align offset has one open end and one closed end, said offset in closed end being horizontally across said first channel and said second channel, with a predetermined distance to said gate.

3. The structure of claim 1, wherein said offset is 0.3 to 0.4 μ

m long.

4. A Load element of SRAM, comprising:

a thin film transistor, wherein said thin film transistor comprises a notched gate structure so that at least one interstice is defined within, source/drain regions beside said notched gate structure and channel regions above said notched gate structure; and

at least one offset region inside said interstice.

5. A Load element of SRAM, comprising:

a gate, wherein said gate is a broach-like structure so that at least one interstice is defined within;

a dielectric layer adjoined with said gate;

a polysilicon layer adjoined with said dielectric layer and crossed to said gate and said interstice, comprising at least one undoped region in said interstice; and

wherein said undoped region is served as an offset structure.

6. A Load element of SRAM, comprising;

a gate having at least one gap within so that at least one interstice is defined inside;

a dielectric layer adjoined with said gate;

a polysilicon layer adjoined with said dielectric layer and crossed to said gate and said interstice;

comprising at least one undoped region in said interstice; and

wherein said undoped region is served as an offset structure.