Apparatus for detecting defect sizes in polysilicon and source-drain semiconductor devices and method for making the same

• US 5,821,765 A
• Filed: 07/24/1997
• Issued: 10/13/1998
• Est. Priority Date: 06/07/1995
• Status: Expired due to Fees

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Ling, Zhi-Min, Lin, Yung-Tao, Shiau, Ying
• Primary Examiner(s): Karlsen, Ernest F.
• Assistant Examiner(s): KOBERT, RUSSELL MARC
• Application Number:
  US08/900,013
• Time in Patent Office: 446 Days
• Field of Search: 324/765, 324/158.1, 324/763, 324/716, 324/537
• US Class Current: 324/762.09
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An apparatus and method for detecting defect sizes in polysilicon and source-drain semiconductor devices and methods for making the same. Implemented is a double bridge test structure that includes a resistor path of first semiconductor material, such as doped silicon comprising a plurality of strip segments and with interconnection segments. A plurality of strips of second semiconductor material having a substantially lower resistivity are connected to form parallel circuit interconnections with the corresponding strip segments. The test structure is formed by masking techniques wherein a prescribed mask region enables portions of the silicon resistor or deposited polysilicon to be selectively silicided to form silicide and polycide, respectively. One embodiment for testing for defects in a polysilicon layer uses polycide as the low-resistivity strips, enabling the testing of open and short-circuit defects. A second embodiment selectively suicides exposed portions of a source-drain resistor, thereby enabling testing for defects in a source-drain layer of a metal oxide semiconductor. Defect sizes are determined by comparing the measured resistance values with predetermined width and spacings of the strips.

Claims

1. A method for detecting spot defect sizes on a semiconductor, comprising the steps of:

providing a double bridge structure having a resistor meander of first semiconductor material formed on said semiconductor and comprising a plurality of parallel strip segments of first resistivity having predetermined width and spacing and interconnection segments each connecting respective ends of an adjacent pair of the strip segments, a plurality of strips of second semiconductor material of second resistivity and connected to corresponding strip segments, respectively, first and second electrodes connected to first and second ends of said resistor meander, respectively, and third and fourth electrodes for measuring a resistance value of one of said interconnection segments;

measuring said resistance value of said interconnection segments between said third and fourth electrodes;

measuring a resistance value between said first and second electrodes; and

calculating a ratio between a measured resistance value of said interconnection segments and a measured resistance value between said first and second electrodes, said ratio determining a spot defect size in accordance with said predetermined width and spacing.

2. A method as recited in claim 1, wherein said double bridge structure further comprises a plurality of local interconnecting sections formed of a silicide and disposed at ends of said strip segments, respectively, said spot defect causing a short or open circuit condition in said double bridge structure.

3. A method as recited in step 1, wherein said first semiconductor material is a source-drain resistor of a MOSFET, and said second semiconductor material is a silicide formed on said source-drain resistor, said defect causing a bridging in said MOSFET.

4. A method for detecting defect sizes on a semiconductor, comprising:

providing a semiconductor structure having;

(1) a resistor path of first semiconductor material formed on said semiconductor and comprising a plurality of parallel strip segments and interconnection segments each connecting respective ends of an adjacent pair of the strip segments, said first semiconductor material having a first resistivity,

(2) a plurality of strips of second semiconductor material corresponding to said strip segments of said resistor path to form strip segments having parallel paths of said first and second resistivities, respectively, said second semiconductor material having a second resistivity lower than said first resistivity;

(3) first and second electrodes formed of said second semiconductor material and electrically connected to two of said strips corresponding to each end of said resistor path, and

(4) third and fourth electrodes formed of said second semiconductor material configured for determining a resistivity value for said interconnection segments;

measuring the resistivity value of the interconnection segments between the third and fourth electrodes;

measuring a resistance value between the first and second electrodes; and

comparing the measured resistivity value of the interconnection segments to the measured resistance value between the first and second electrodes to detect a number of the adjacent strip segments encountering a spot defect.

5. The method of claim 4, wherein the comparing step comprises testing for a short circuit caused by the spot defect.

6. The method of claim 4, wherein the comparing step comprises testing for an open circuit caused by the spot defect.

7. The method of claim 4, wherein the providing step comprises:

forming the first semiconductor material as a source-drain resistor; and

forming the second semiconductor material strips by selective silicidation of the source-drain resistor.

8. The method of claim 7, wherein the providing step comprises forming the second semiconductor material strips by annealing deposited silicon with a refractory metal silicide.