Low voltage CMOS logic circuit with threshold voltage control

• US 5,821,769 A
• Filed: 04/18/1996
• Issued: 10/13/1998
• Est. Priority Date: 04/21/1995
• Status: Expired due to Term

• Current Assignee: Nippon Telegraph and Telephone Corporation
• Original Assignee: Nippon Telegraph and Telephone Corporation
• Inventors: Douseki, Takakuni
• Primary Examiner(s): SANTAMAURO, JON P
• Application Number:
  US08/634,552
• Time in Patent Office: 908 Days
• Field of Search: 326/31, 326/33-34, 326/112, 326/119, 326/121, 326/81, 326/17, 326/15, 326/27, 326/83, 326/86, 327/534, 327/537, 327/333
• US Class Current: 326/34
• CPC Class Codes: H01L 27/0218 of field effect structures
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply
• CPC Class Codes: H03K 19/00361 in field effect transistor circuits

Abstract

A MOSFET circuit achieving high speed operation and low power consumption for a wide supply voltage range. MOSFET circuits are connected between a low threshold voltage CMOS circuit and a supply voltage and ground, as a power controller for switching power supply in response to sleep/active modes. High threshold voltage MOSFETs in the MOSFET circuits are gate biased by low threshold voltage MOSFETs, thereby preventing a current from flowing across the backgate terminal and the source terminal.

Claims

1. A MOSFET circuit comprising:

a first MOSFET having a first threshold voltage; and

a second MOSFET having a second threshold voltage lower than or equal to said first threshold voltage, said second MOSFET having a gate electrode and a first main current electrode connected to a backgate electrode of said first MOSFET, and a second main current electrode connected to an external signal, wherein said second threshold voltage is lower than said first threshold.

2. A CMOS logic circuit including a series connection of a load transistor and a driver transistor, one of said driver transistor and said load transistor including a first MOSFET circuit, said first MOSFET circuit comprising:

a first MOSFET having a first threshold voltage, and being connected to the other of said driver transistor and said load transistor; and

a second MOSFET having a second threshold voltage lower than said first threshold voltage, and having a gate electrode and a first main current electrode connected to a backgate electrode of said first MOSFET, and a second main current electrode connected to a gate electrode of said first MOSFET.

3. The CMOS logic circuit as claimed in claim 2, wherein the other of said driver transistor and said load transistor is a MOSFET, and said CMOS logic circuit is a CMOS inverter.

4. The CMOS logic circuit as claimed in claim 2, wherein said load transistor comprises M (M is an integer greater than one) MOSFETs connected in series, and said driver transistor comprises M said first MOSFET circuits connected in parallel, and said CMOS logic circuit is a NOR circuit.

5. The CMOS logic circuit as claimed in claim 2, wherein said load transistor comprises M (M is an integer greater than one) MOSFETs connected in parallel, and said driver transistor comprises M said first MOSFET circuits connected in series, and said CMOS logic circuit is a NAND circuit.

6. The CMOS logic circuit as claimed in claim 2, wherein the other of said driver transistor and said load transistor includes a second MOSFET circuit, said second MOSFET comprising:

a third MOSFET having a third threshold voltage, and being connected with said first MOSFET circuit in series; and

a fourth MOSFET having a fourth threshold voltage lower than said third threshold voltage, and having a gate electrode and a first main current electrode connected to a backgate electrode of said third MOSFET, and a second main current electrode connected to a gate electrode of said third MOSFET.

7. The CMOS logic circuit as claimed in claim 6, wherein said CMOS logic circuit is a CMOS inverter.

8. The CMOS logic circuit as claimed in claim 6, wherein said driver transistor comprises M (M is an integer greater than one) said first MOSFET circuits connected in parallel, and said load transistor comprises M said second MOSFET circuits connected in series, and said CMOS logic circuit is a NOR circuit.

9. The CMOS logic circuit as claimed in claim 6, wherein said driver transistor comprises M (M is an integer greater than one) said first MOSFET circuits connected in series, and said load transistor comprises M said second MOSFET circuits connected in parallel, and said CMOS logic circuit is a NAND circuit.

10. The CMOS logic circuit as claimed in claim 2, wherein each MOSFET of said CMOS logic circuit is a SOIFET which is formed on a SOI (Semiconductor On Insulator) substrate.

11. The CMOS logic circuit as claimed in claim 10, wherein carrier concentration of a body of said second MOSFET is controlled such that said body becomes a fully depleted state.

12. The CMOS logic circuit as claimed in claim 10, wherein carrier concentration of a body of said second MOSFET is controlled such that said body becomes a partially depleted state.

13. A buffer circuit including a first CMOS inverter and a second CMOS inverter alternately connected in cascade,

wherein a load transistor of said first CMOS inverter comprises:

a first MOSFET having a first threshold voltage, and being connected with a driver transistor of said first CMOS inverter in series; and

a second MOSFET having a second threshold voltage lower than said first threshold voltage, and having a gate electrode and a first main current electrode connected to a backgate electrode of said first MOSFET, and a second main current electrode connected to a gate electrode of said first MOSFET, and

wherein a driver transistor of said second CMOS inverter comprises;

a third MOSFET having a third threshold voltage, and being connected with a load transistor of said second CMOS inverter in series; and

a fourth MOSFET having a fourth threshold voltage lower than said third threshold voltage, and having a gate electrode and a first main current electrode connected to a backgate electrode of said third MOSFET, and a second main current electrode connected to a gate electrode of said third MOSFET.

14. A CMOS logic circuit including a low threshold CMOS logic circuit and at least one switching circuit, said low threshold CMOS logic circuit including MOSFETs with a threshold voltage lower than a first threshold voltage, and said switching circuit being connected between a power supply terminal of said low threshold CMOS logic circuit and a power supply, wherein said switching circuit comprises:

a first MOSFET having said first threshold voltage, and being connected between said power supply and said power supply terminal of said low threshold CMOS logic circuit; and

a second MOSFET having a second threshold voltage lower than said first threshold voltage, and having a gate electrode and a first main current electrode connected to a backgate electrode of said first MOSFET, and a second main current electrode connected to a gate electrode of said first MOSFET.

15. The CMOS logic circuit as claimed in claim 14, wherein said switching circuit is connected between a high potential terminal of said power supply and a high potential power supply terminal of said low threshold CMOS logic circuit.

16. The CMOS logic circuit as claimed in claim 14, wherein said switching circuit is connected between a low potential terminal of said power supply and a low potential power supply terminal of said low threshold CMOS logic circuit.

17. The CMOS logic circuit as claimed in claim 15, wherein said switching circuit is further connected between a low potential terminal of said power supply and a low potential power supply terminal of said low threshold CMOS logic circuit.

18. The CMOS logic circuit as claimed in claim 14, wherein said CMOS logic circuit is switched between a sleep mode and an active mode by a sleep signal externally fed, and further comprises a first buffer connected to a non-inverted sleep signal input terminal of said CMOS logic circuit, and a second buffer connected to an inverted sleep signal input terminal of said CMOS logic circuit,

wherein said first buffer comprises a first CMOS inverter and a second CMOS inverter alternately connected in cascade, and a load transistor of said first CMOS inverter comprises:

a first MOSFET having said first threshold voltage, and being connected with a driver transistor of said first CMOS inverter in series; and

a second MOSFET having a second threshold voltage lower than said first threshold voltage, and having a gate electrode and a first main current electrode connected to a backgate electrode of said first MOSFET, and a second main current electrode connected to a gate electrode of said first MOSFET,

wherein a driver transistor of said second CMOS inverter comprises;

a third MOSFET having a third threshold voltage, and being connected with a load transistor of said second CMOS inverter in series; and

a fourth MOSFET having a fourth threshold voltage lower than said third threshold voltage, and having a gate electrode and a first main current electrode connected to a backgate electrode of said third MOSFET, and a second main current electrode connected to a gate electrode of said third MOSFET, and

wherein said second buffer comprises said second CMOS inverter and said first CMOS inverter alternately connected in cascade.

19. The CMOS logic circuit as claimed in claim 14, wherein said CMOS logic circuit is switched between a sleep mode and an active mode by a sleep signal externally fed, and further comprises a buffer connected to a non inverted sleep signal input terminal of said CMOS logic circuit,

wherein said buffer comprises a first CMOS inverter and a second CMOS inverter alternately connected in cascade, and a load transistor of said first CMOS inverter comprises:

a first MOSFET having said first threshold voltage, and being connected with a driver transistor of said first CMOS inverter in series; and

a second MOSFET having a second threshold voltage lower than said first threshold voltage, and having a gate electrode and a first main current electrode connected to a backgate electrode of said first MOSFET, and a second main current electrode connected to a gate electrode of said first MOSFET, and

wherein a driver transistor of said second CMOS inverter comprises;

a third MOSFET having a third threshold voltage, and being connected with a load transistor of said second CMOS inverter in series; and

a fourth MOSFET having a fourth threshold voltage lower than said third threshold voltage, and having a gate electrode and a first main current electrode connected to a backgate electrode of said third MOSFET, and a second main current electrode connected to a gate electrode of said third MOSFET.

20. The CMOS logic circuit as claimed in claim 14, wherein said CMOS logic circuit is switched between a sleep mode and an active mode by a sleep signal externally fed, and further comprises a buffer connected to an inverted sleep signal input terminal of said CMOS logic circuit,

wherein said buffer comprises a first CMOS inverter and a second CMOS inverter alternately connected in cascade, wherein a driver transistor of said first CMOS inverter comprises:

a first MOSFET having said first threshold voltage, and being connected with a load transistor of said first CMOS inverter in series; and

a second MOSFET having a second threshold voltage lower than said first threshold voltage, and having a gate electrode and a first main current electrode connected to a backgate electrode of said first MOSFET, and a second main current electrode connected to a gate electrode of said first MOSFET, and

wherein a load transistor of said second CMOS inverter comprises;

a third MOSFET having a third threshold voltage, and being connected with a driver transistor of said second CMOS inverter in series; and

a fourth MOSFET having a fourth threshold voltage lower than said third threshold voltage, and having a gate electrode and a first main current electrode connected to a backgate electrode of said third MOSFET, and a second main current electrode connected to a gate electrode of said third MOSFET.

21. The CMOS logic circuit as claimed in claim 14, wherein each MOSFET of said CMOS logic circuit is a SOIFET which is formed on a SOI (Semiconductor On Insulator) substrate.

22. The CMOS logic circuit as claimed in claim 21, wherein carrier concentration of a body of each of said low threshold MOSFET is controlled such that said body becomes a fully depleted state.

23. The CMOS logic circuit as claimed in claim 21, wherein carrier concentration of a body of each said low threshold MOSFET is controlled such that said body becomes a partially depleted state.

24. A CMOS logic circuit comprising:

an internal CMOS logic circuit including a set of M (M is an integer equal to or greater than one) driver transistors and a set of M load transistors, said internal CMOS logic circuit changing its operation mode in response to an external control signal;

a first MOSFET connected to a first MOSFET circuit constituting one of said set of driver transistors and said set of load transistors, wherein said first MOSFET has a same channel type as said first MOSFET circuit, and comprises a gate electrode and a first main current electrode connected to a backgate electrode of said first MOSFET circuit, and a second main current electrode connected to said external control signal; and

a second MOSFET connected to a second MOSFET circuit constituting the other of said set of driver transistors and said set of load transistors, wherein said second MOSFET has a same channel type as said second MOSFET circuit, and comprises a gate electrode and a first main current electrode connected to a backgate electrode of said second MOSFET circuit, and a second main current electrode connected to an inverted signal of said external control signal.

25. The CMOS logic circuit as claimed in claim 24, wherein a threshold voltage of each of said first MOSFET and said second MOSFET is lower than a threshold voltage of MOSFETs included in said internal CMOS logic circuit.

26. The CMOS logic circuit as claimed in claim 25, wherein each MOSFET of said CMOS logic circuit is a SOIFET which is formed on a SOI (Semiconductor on Insulator) substrate, and wherein carrier concentration of a body of each of said low threshold MOSFET is controlled such that said body becomes a fully depleted state.

27. The CMOS logic circuit as claimed in claim 25, wherein each MOSFET of said CMOS logic circuit is a SOIFET which is formed on a SOI (Semiconductor on Insulator) substrate, and wherein carrier concentration of a body of each of said low threshold MOSFET is controlled such that said body becomes a partially depleted state.

28. A CMOS logic circuit comprising:

an internal CMOS logic circuit including a set of M (M is an integer equal to or greater than one) driver transistors and a set of M load transistors, said internal CMOS logic circuit changing its operation mode in response to an external control signal; and

a first MOSFET connected to a first MOSFET circuit constituting one of said set of driver transistors and said set of load transistors, wherein said first MOSFET has a same channel type as said first MOSFET circuit, and comprises a gate electrode and a first main current electrode connected to a backgate electrode of said first MOSFET circuit, and a second main current electrode connected to said external control signal;

wherein said internal CMOS logic circuit comprises a memory cell, and said control signal is a word line signal.