Look-up table based logic element with complete permutability of the inputs to the secondary signals

• US 5,821,773 A
• Filed: 09/06/1995
• Issued: 10/13/1998
• Est. Priority Date: 09/06/1995
• Status: Expired due to Term

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group), Altera Corporation (Intel Corporation)
• Original Assignee: Quickturn Design Systems Incorporated (Cadence Group), Altera Corporation (Intel Corporation)
• Inventors: Patel, Rakesh H., Butts, Michael R., Sample, Stephen P., Norman, Kevin A.
• Primary Examiner(s): Tokar, Michael J.
• Assistant Examiner(s): ROSEEN, RICHARD R
• Application Number:
  US08/524,698
• Time in Patent Office: 1,133 Days
• Field of Search: 326/16, 326/39, 326/40, 371/22.1, 371/22.3
• US Class Current: 326/39
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables

Abstract

A logic element for a programmable logic device. The logic element includes a look-up table (400) for implementing logical functions, a programmable delay block (415), a storage block (430) configurable as a latch or a flip-flop, and a diagnostic shadow latch (435). A plurality of inputs (410) to the logic element and complements of these inputs are available to control the secondary functions of the storage block (430).

Claims

1. In a programmable logic device, a logic element comprising:

a look-up table for implementing logical functions coupled to a multiplexer;

a storage block, coupled to said look-up table, wherein said storage block stores an output of said look-up table;

a first plurality of inputs, programmably coupled to said multiplexer and programmably coupled to said storage block;

a second plurality of inputs, programmably coupled to said storage block, wherein said second plurality of inputs are complements of said first plurality of inputs;

a combinatorial output, coupled to said look-up table; and

a registered output, coupled to said storage block.

2. In a programmable logic device, a logic element comprising:

a look-up table for implementing logical functions coupled to a multiplexer;

a storage block, programmably coupled to said look-up table, wherein said storage block stores an output of said look-up table, wherein said storage block comprises clock enable, clear, preset, and clock inputs;

a first plurality of inputs, programmably coupled to said multiplexer and programmably coupled to said clock enable, clear, preset, and clock inputs; and

a second plurality of inputs, programmably coupled to said clock enable, clear, preset, and clock inputs, wherein said second plurality of inputs are complements of said first plurality of inputs;

a combinatorial output, coupled to said look-up table; and

a registered output, coupled to said storage block.

3. A logic element for a programmable logic device comprising:

a programmable function generator for implementing logical functions; and

a programmable delay block, coupled to said programmable function generator, wherein said programmable delay block programmably delays an output from said programmable function generator.

4. The logic element of claim 3 further comprising:

a storage block for storing said output from said programmable function generator, wherein said delay block is coupled between said programmable function generator and said storage block, wherein said programmable delay block programmably delays a signal passed from said programmable function generator to said storage block.

5. The logic element of claim 4 further comprising:

a multiplexer, coupled between said delay block and said storage block, wherein said multiplexer selectively couples said delay block to said storage block.

6. The logic element of claim 5 wherein said multiplexer selectively couples a secondary logic block to said storage block, wherein a path from said secondary logic block through said multiplexer to said storage block does not pass through said programmable delay block.

7. The logic element of claim 6 wherein said multiplexer selectively couples a diagnostic shadow latch to said storage block, wherein a path from said diagnostic shadow latch through said multiplexer to said storage block does not pass through said programmable delay block.

8. The logic element of claim 4 further comprising:

a multiplexer, wherein said multiplexer selectively couples said programmable function generator to an output of said logic element, wherein an output path from said programmable function generator to said multiplexer does not pass through said programmable delay block.

9. The logic element of claim 8 wherein said multiplexer selectively couples said storage block to an output of said logic element, wherein an output path from said storage block to said multiplexer does not pass through said programmable delay block.

22. A system comprising a programmable logic device having a logic element as recited in claim 3.

10. A logic element for a programmable logic device comprising:

a programmable function generator for implementing logical functions;

a diagnostic shadow latch, coupled to a configuration loading pin of said programmable function generator, wherein said diagnostic shadow latch stores and provides diagnostic data; and

a storage block coupled to an output of said programmable function generator and to said diagnostic shadow latch.

11. A logic element in a programmable logic device comprising:

a programmable function generator for implementing logical functions;

a diagnostic shadow latch, coupled to a plurality of configuration loading pins of said programmable function generator, wherein said diagnostic shadow latch stores and provides diagnostic data; and

a storage block, coupled to said programmable function generator, wherein said storage block stores an output of said programmable function generator, wherein said diagnostic shadow latch is coupled to an input of said storage block and an output of said storage block.

12. A logic element for a programmable logic device comprising:

a programmable function generator for implementing logical functions;

a storage block, coupled to said programmable function generator, said storage block for storing said output from said programmable function generator; and

a diagnostic shadow latch, coupled to an input of said storage block and an output of said storage block, wherein said diagnostic shadow latch stores and provides diagnostic data.

13. The logic element of claim 12 further comprising:

a multiplexer, coupled between said programmable function generator and said storage block and coupled between said diagnostic shadow latch and said storage block, wherein said multiplexer selectively couples said programmable function generator and said diagnostic shadow latch to said storage block.

14. The logic element of claim 13 further comprising:

a plurality of control inputs, coupled to control said multiplexer and said diagnostic shadow latch.

15. A logic element for a programmable logic device comprising:

a programmable function generator for implementing logical functions;

a secondary logic block, coupled to said programmable function generator, wherein said secondary logic block implements logical functions; and

a storage block, coupled to said programmable function generator and said secondary logic block, wherein said storage block selectively stores an output from said programmable function generator or an output from said secondary logic block.

16. The logic element of claim 15 further comprising:

a diagnostic shadow latch, coupled to said storage block, wherein said storage block selectively stores an output from said diagnostic shadow latch.

17. A logic element for a programmable logic device comprising:

a programmable function generator for implementing logical functions;

a secondary logic block, coupled to said programmable function generator, wherein said secondary logic block implements logical functions;

a first plurality of inputs, coupled to said programmable function generator and said secondary logic block; and

a second plurality of inputs, coupled to said secondary logic block, wherein said second plurality of inputs are complements of said first plurality of inputs.

18. The logic element of claim 17 further comprising:

a storage block, coupled to selectively store an output of said programmable function generator or an output of said secondary logic block;

wherein a selected one of said first plurality of inputs controls a preset input of said storage block and said secondary logic block; and

wherein a selected one of said second plurality of inputs controls said preset input of said storage block and said secondary logic block, wherein said second plurality of inputs are complements of said first plurality of inputs.

19. The logic element of claim 17 further comprising:

a storage block, coupled to selectively store an output of said programmable function generator and an output of said secondary logic block;

wherein a selected one of said first plurality of inputs controls a clear input of said storage block and said secondary logic block; and

wherein a selected one of said second plurality of inputs controls said clear input of said storage block and said secondary logic block, wherein said second plurality of inputs are complements of said first plurality of inputs.

20. A logic element for a programmable logic device, comprising:

a programmable function generator for implementing logical functions;

a secondary logic block, coupled to said programmable function generator, wherein said secondary logic block implements logical functions; and

a storage block, coupled to said programmable function generator and said secondary logic block, said storage block selectively stores an output from said programmable function generator or an output from said secondary logic block, wherein an output of said secondary logic block may be programmably coupled through said storage block to an output of said logic element.

21. A logic element for a programmable logic device, comprising:

a programmable function generator for implementing logical functions;

a secondary logic block, coupled to said programmable function generator, wherein said secondary logic block implements logical functions; and

a storage block, coupled to said programmable function generator and said secondary logic block, said storage block selectively stores an output from said programmable function generator or an output from said secondary logic block, wherein said programmable function generator is coupled to said secondary logic block via a direct path, not passing through said storage block.

23. A logic element for a programmable logic device comprising:

a look-up table for implementing logical functions;

a storage block, coupled to said look-up table, said storage block storing an output from said look-up table, said storage block programmable configurable as a latch in a first mode, wherein said latch is responsive to a level-sensitive input, said storage block programmable configurable as a register in a second mode, wherein said register is responsive to an edge-triggered input;

a combinatorial output, coupled to said look-up table;

a registered output, coupled to said storage block; and

a programmable delay block, coupled between said look-up table and said storage block, said programmable delay block for programmably delaying a signal passed from said look-up table to said storage block.

24. A logic element for a programmable logic device comprising:

a look-up table for implementing logical functions;

a storage block, coupled to said look-up table, said storage block storing an output from said look-up table, said storage block programmable configurable as a latch in a first mode, wherein said latch is responsive to a level-sensitive input, said storage block programmable configurable as a register in a second mode, wherein said register is responsive to an edge-triggered input;

a combinatorial output, coupled to said look-up table;

a registered output, coupled to said storage block;

a first plurality of inputs, programmably coupled to control said look-up table and a control input of said storage block; and

a second plurality of inputs, programmably coupled to control said control input of said storage block, wherein said second plurality of inputs are complements of said first plurality of inputs.

25. The logic element of claim 24, wherein the control input is a preset input of said storage block.

26. The logic element of claim 24, wherein the control input is a clock enable input of said storage block.

27. The logic element of claim 24, wherein the control input is a clock input of said storage block.

28. The logic element of claim 27 further comprising:

a first plurality of clock inputs, programmably coupled to said clock input of said storage block; and

a second plurality of clock inputs, programmably coupled to said clock input of said storage block, wherein said second plurality of clock inputs are complements of said first plurality of clock inputs.

29. The logic element of claim 24, wherein the control input is a clock input of said storage block.

30. A logic element for a programmable logic device comprising:

a look-up table for implementing logical functions;

a storage block, coupled to said look-up table, said storage block storing an output from said look-up table, said storage block programmably configurable as a latch in a first mode, wherein said latch is responsive to a level-sensitive input, said storage block programmable configurable as a register in a second mode, wherein said register is responsive to an edge-triggered input;

a combinatorial output, coupled to said look-up table;

a registered output, coupled to said storage block; and

a diagnostic shadow latch, coupled to said look-up table and said storage block, wherein said diagnostic shadow latch stores and provides diagnostic data.

31. A logic element for a programmable logic device comprising:

a look-up table for implementing logical functions;

a storage block, coupled to said look-up table, said storage block storing an output from said look-up table, said storage block programmable configurable as a latch in a first mode, wherein said latch is responsive to a level-sensitive input, said storage block programmable configurable as a register in a second mode, wherein said register is responsive to an edge-triggered input;

a combinatorial output, coupled to said look-up table;

a registered output, coupled to said storage block; and

a diagnostic shadow latch, coupled to an input of said storage block and an output of said storage block, wherein said diagnostic shadow latch stores and provides diagnostic data.

32. A logic element for a programmable logic device comprising:

a look-up table for implementing logical functions;

a storage block, coupled to said look-up table, said storage block storing an output from said look-up table, said storage block programmably configurable as a latch in a first mode, wherein said latch is responsive to a level-sensitive input, said storage block programmable configurable as a register in a second mode, wherein said register is responsive to an edge-triggered input;

a combinatorial output, coupled to said look-up table;

a registered output, coupled to said storage block; and

a diagnostic shadow latch, coupled to a plurality of configuration loading pins for said look-up table, wherein said diagnostic shadow latch stores and provides diagnostic data.