CMOS high-speed differential to single-ended converter circuit

• US 5,821,809 A
• Filed: 05/23/1996
• Issued: 10/13/1998
• Est. Priority Date: 05/23/1996
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Dreps, Daniel Mark, Boerstler, David William
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): ENGLUND, TERRY LEE
• Application Number:
  US08/652,056
• Time in Patent Office: 873 Days
• Field of Search: 326/66, 326/77, 326/115, 330/257, 330/258, 330/260, 330/261, 330/253, 330/254, 330/295, 327/52, 327/54, 327/65, 327/67, 327/560, 327/562, 327/563, 327/56, 327/58, 327/70, 327/80, 327/81, 327/333, 327/407, 327/53, 327/66, 327/77, 327/78, 327/79, 327/85, 327/87, 327/88, 327/89 , 327/69, 327/374, 327/375, 327/376, 327/377
• US Class Current: 327/563
• CPC Class Codes: H03F 2203/45454 the CSC comprising biasing means controlled by the input signal
• CPC Class Codes: H03F 2203/45646 the LC comprising an extra current source
• CPC Class Codes: H03F 2203/45658 the LC comprising two diodes of current mirrors
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit
• CPC Class Codes: H03K 19/018528 with at least one differential stage

Abstract

A CMOS differential to single-ended converter is implemented. A differential input stage comprised of a pair of N-channel transistors draws current through two fixed current P-channel load transistors. A first N-channel differential transistor provides negative feedback bias control of a current source transistor coupled to the differential input stage. The negative feedback control provides increased current gain in the second N-channel transistor, which drives a CMOS inverter to a full rail-to-rail voltage swing on its output.

Claims

1. A converter circuit, comprising:

a first input terminal for receiving a first differential input signal;

a second input terminal for receiving a second differential input signal;

an output terminal; and

a differential input stage, comprising;

a first current load device coupled to a high voltage rail, wherein a first load current through said first current load device is determined by a static reference voltage;

a second current load device coupled to said high voltage rail, wherein a second load current through said second current load device is controlled by said static reference voltage;

a first input means coupled to said first current load device and said first input terminal for receiving said first differential input signal and controlling a first branch current through a first branch of said differential input stage, said first input means generating an output signal for transmission to said output terminal; and

a second input means coupled to said second current load device and said second input terminal for receiving said second differential input signal, controlling a second branch current through a second branch of said differential input stage, and generating a control signal for controlling a third current in a current source device coupled to a low voltage rail and to said differential input stage, wherein said control signal is out-of-phase with said output signal.

2. The converter circuit in claim 1 wherein said first current load device is a first PFET transistor having a gate coupled to said static reference voltage and said second current load device is a second PFET transistor having a gate coupled to said static reference voltage.

3. The converter circuit in claim 1 further comprising a CMOS inverter coupled to said output terminal for receiving said output signal and generating a full-swing output signal having an upper limit substantially equal to a voltage level of said high voltage rail and a lower limit substantially equal to a voltage level of said low voltage rail.

4. The converter circuit in claim 1 further comprising a first clamping device for clamping a lower limit of said output signal at a predetermined voltage level below said high voltage rail.

5. The converter circuit in claim 4 further comprising a second clamping device for clamping a lower limit of said control signal at said predetermined voltage level below said high voltage rail.

6. A converter circuit, comprising:

a first input terminal for receiving a first differential input signal;

a second input terminal for receiving a second differential input signal;

an output terminal; and

a differential input stage, comprising;

a first current load device coupled to a high voltage rail, wherein a first load current through said first current load device is determined by a static reference voltage;

a second current load device coupled to said high voltage rail, wherein a second load current through said second current load device is controlled by said static reference voltage;

a first input means coupled to said first current load device and said first input terminal for receiving said first differential input signal and controlling a first branch current through a first branch of said differential input stage, said first input means generating an output signal for transmission to said output terminal; and

a second input means coupled to said second current load device and said second input terminal for receiving said second differential input signal, controlling a second branch current through a second branch of said differential input stage, and generating a control signal for controlling a third current in a current source device coupled to a low voltage rail and to said differential input stage, wherein an increase in said second branch current through said second input means causes a decrease in said first branch current, and wherein a magnitude of said decrease is greater than a magnitude of said increase.

7. The converter circuit in claim 6 wherein a decrease in said second branch current through said second input means causes an increase in said first branch current, wherein a magnitude of said increase is greater than a magnitude of said decrease.

8. A converter circuit, comprising:

a first input terminal for receiving a first differential input signal;

a second input terminal for receiving a second differential input signal;

an output terminal; and

a differential input stage comprising;

a first current load device coupled to a high voltage rail, wherein a first load current through said first current load device is determined by a static reference voltage;

a second current load device coupled to said high voltage rail, wherein a second load current through said second current load device is controlled by said static reference voltage;

a first input means coupled to said first current load device and said first input terminal for receiving said first differential input signal and controlling a first branch current through a first branch of said differential input stage, said first input means generating an output signal for transmission to said output terminal, wherein an amplitude of said output signal is greater than an amplitude of said first input differential signal; and

a second input means coupled to said second current load device and said second input terminal for receiving said second differential input signal, controlling a second branch current through a second branch of said differential input stage, and generating a control signal for controlling a third current in a current source device coupled to a low voltage rail and to said differential input stage.

9. A converter circuit, comprising:

a first input terminal for receiving a first differential input signal;

a second input terminal for receiving a second differential input signal;

an output terminal; and

a differential input stage, comprising;

a first current load device coupled to a high voltage rail, wherein a first load current through said first current load device is determined by a static reference voltage;

a second current load device coupled to said high voltage rail, wherein a second load current through said second current load device is controlled by said static reference voltage;

a first input means coupled to said first current load device and said first input terminal for receiving said first differential input signal and controlling a first branch current through a first branch of said differential input stage, said first input means generating an output signal for transmission to said output terminal, wherein an amplitude of said output signal is greater than an amplitude of a difference between said first differential input signal and said second differential input signal; and

a second input means coupled to said second current load device in said second input terminal for receiving said second differential input signal, controlling a second branch current through a second branch of said differential input stage, and generating a control signal for controlling a third current in a current source device coupled to a low voltage rail and to said differential input stage.

10. An integrated circuit comprising:

a first block of processing circuitry, said first block of processing circuitry generating a pair of differential signals on a first differential output terminal and a second differential output terminal;

a converter circuit, comprising;

a first input terminal coupled to said first differential output terminal for receiving a first differential input signal;

a second input terminal coupled to said second differential output terminal for receiving a second differential input signal;

an output terminal;

a differential input stage comprising;

a first current load device coupled to a high voltage rail, wherein a first load current through said first current load device is determined by a static reference voltage;

a second current load device coupled to said high voltage rail, wherein a second load current through said second current load device is controlled by said static reference voltage;

a first input means coupled to said first current load device and said first input terminal for receiving said first differential input signal and controlling a first branch current through a first branch of said differential input stage, said first input means generating an output signal for transmission to said output terminal; and

a second input means coupled to said second current load device and said second input terminal for receiving said second differential input signal, controlling a second branch current through a second branch of said differential input stage, and generating a control signal for controlling a third current in a current source device coupled to a low voltage rail and to said differential input stage, wherein said control signal is out-of-phase with said output signal; and

a CMOS inverter coupled to said output terminal for receiving said output signal and generating a full-swing output signal having an upper limit substantially equal to a voltage level of said high voltage rail and a lower limit substantially equal to a voltage level of said low voltage rail.

11. The integrated circuit in claim 10 wherein said first current load device is a first PFET transistor having a gate coupled to said static reference voltage and said second current load device is a second PFET transistor having a gate coupled to said static reference voltage.

12. The integrated circuit in claim 10 further comprising a first clamping device for clamping a lower limit of said output signal at a predetermined voltage level below said high voltage rail.

13. The integrated circuit in claim 12 further comprising a second clamping device for clamping a lower limit of said control signal at said predetermined voltage level below said high voltage rail.

14. An integrated circuit comprising:

a first block of processing circuitry, said first block of processing circuitry generating a pair of differential signals on a first differential output terminal and a second differential output terminal;

a converter circuit, comprising;

a first input terminal coupled to said first differential output terminal for receiving a first differential input signal;

a second input terminal coupled to said second differential output terminal for receiving a second differential input signal;

an output terminal;

a differential input stage comprising;

a first current load device coupled to a high voltage rail, wherein a first load current through said first current load device is determined by a static reference voltage;

a second current load device coupled to said high voltage rail, wherein a second load current through said second current load device is controlled by said static reference voltage;

a first input means coupled to said first current load device and said first input terminal for receiving said first differential input signal and controlling a first branch current through a first branch of said differential input stage, said first input means generating an output signal for transmission to said output terminal; and

a second input means coupled to said second current load device and said second input terminal for receiving said second differential input signal, controlling a second branch current through a second branch of said differential input stage, and generating a control signal for controlling a third current in a current source device coupled to a low voltage rail and to said differential input stage, wherein an increase in said second branch current through said second input means causes a decrease in said first branch current, wherein a magnitude of said decrease is greater than a magnitude of said increase; and

a CMOS inverter coupled to said output terminal for receiving said output signal and generating a full-swing output signal having an upper limit substantially equal to a voltage level of said high voltage rail and a lower limit substantially equal to a voltage level of said low voltage rail.

15. The integrated circuit in claim 14 wherein a decrease in said second branch current through said second input means causes an increase in said first branch current, wherein a magnitude of said increase is greater than a magnitude of said decrease.

16. An integrated circuit comprising:

a first block of processing circuitry, said first block of processing circuitry generating a pair of differential signals on a first differential output terminal and a second differential output terminal;

a converter circuit, comprising;

a first input terminal coupled to said first differential output terminal for receiving a first differential input signal;

a second input terminal coupled to said second differential output terminal for receiving a second differential input signal;

an output terminal;

a differential input stage comprising;

a first current load device coupled to a high voltage rail, wherein a first load current through said first current load device is determined by a static reference voltage;

a second current load device coupled to said high voltage rail, wherein a second load current through said second current load device is controlled by said static reference voltage;

a first input means coupled to said first current load device and said first input terminal for receiving said first differential input signal and controlling a first branch current through a first branch of said differential input stage, said first input means generating an output signal for transmission to said output terminal, wherein an amplitude of said output signal is greater than an amplitude of said first input differential signal; and

a second input means coupled to said second current load device and said second input terminal for receiving said second differential input signal, controlling a second branch current through a second branch of said differential input stage, and generating a control signal for controlling a third current in a current source device coupled to a low voltage rail and to said differential input stage, wherein an increase in said second branch current through said second input means causes a decrease in said first branch current; and

a CMOS inverter coupled to said output terminal for receiving said output signal and generating a full-swing output signal having an upper limit substantially equal to a voltage level of said high voltage rail and a lower limit substantially equal to a voltage level of said low voltage rail.

17. An integrated circuit comprising:

a first block of processing circuitry, said first block of processing circuitry generating a pair of differential signals on a first differential output terminal and a second differential output terminal;

a converter circuit, comprising;

a first input terminal coupled to said first differential output terminal for receiving a first differential input signal;

a second input terminal coupled to said second differential output terminal for receiving a second differential input signal;

an output terminal;

a differential input stage comprising;

a first current load device coupled to a high voltage rail, wherein a first load current through said first current load device is determined by a static reference voltage;

a second current load device coupled to said high voltage rail, wherein a second load current through said second current load device is controlled by said static reference voltage;

a first input means coupled to said first current load device and said first input terminal for receiving said first differential input signal and controlling a first branch current through a first branch of said differential input stage, said first input means generating an output signal for transmission to said output terminal, wherein an amplitude of said output signal is greater than an amplitude of a difference between said first differential input signal and said second differential input signal; and

a second input means coupled to said second current load device and said second input terminal for receiving said second differential input signal, controlling a second branch current through a second branch of said differential input stage, and generating a control signal for controlling a third current in a current source device coupled to a low voltage rail and to said differential input stage; and

a CMOS inverter coupled to said output terminal for receiving said output signal and generating a full-swing output signal having an upper limit substantially equal to a voltage level of said high voltage rail and a lower limit substantially equal to a voltage level of said low voltage rail.