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Systems, methods and computer program products for prediction of defect-related failures in integrated circuits

  • US 5,822,218 A
  • Filed: 08/27/1996
  • Issued: 10/13/1998
  • Est. Priority Date: 08/27/1996
  • Status: Expired due to Term
First Claim
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1. A method of predicting defect-related failures in integrated circuits produced by an integrated circuit fabrication process according to a circuit layout for an integrated circuit design, the method comprising the following steps which are performed in a data processing system:

  • identifying objects in the circuit layout, each object having a location in the circuit layout and a reliability connectivity in the integrated circuit design;

    generating sample object defects for the identified objects, each sample object defect representing a defect induced in an object by the integrated circuit fabrication process, each sample object defect having a defect magnitude associated therewith;

    identifying an accelerated life defect influence model for each sample object defect, each accelerated life defect influence model relating the lifetime of an object to the defect magnitude of a defect in the object;

    generating sample object lifetimes from the defect magnitudes associated with the sample object defects according to the corresponding identified accelerated life defect influence models; and

    generating a prediction of the reliability of integrated circuits produced by the integrated circuit fabrication process according to the circuit layout, from the sample object lifetimes according to the reliability connectivity of the associated objects in the integrated circuit design.

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