Self-calibrating data processors and methods for calibrating same

• US 5,822,225 A
• Filed: 09/21/1994
• Issued: 10/13/1998
• Est. Priority Date: 09/21/1994
• Status: Expired due to Term

• Current Assignee: Ericsson Raynet Corporation A Delaware General Partnership (Telefonaktiebolaget LM Ericsson)
• Original Assignee: Ericsson Raynet Corporation
• Inventors: Quaderer, James, Sanders, Kirk
• Primary Examiner(s): Cosimano, Edward R.
• Assistant Examiner(s): MILLER, CRAIG S
• Application Number:
  US08/310,244
• Time in Patent Office: 1,483 Days
• Field of Search: 364/571.01, 364/571.02, 364/571.04-571.06, 341/110, 341/126, 341/133, 341/140, 341/144, 341/158, 341/159, 323/312-315
• US Class Current: 702/89
• CPC Class Codes: G01R 35/00 Testing or calibrating of apparatus covered by the other groups of this subclass
• CPC Class Codes: H03M 1/1028 at two points of the transfer characteristic, i.e. by adjusting two reference values, e.g. offset and gain error gain setting for range control H03M1/18
• CPC Class Codes: H03M 1/1215 using time-division multiplexing

Abstract

Highly accurate, self-calibrating data processors and methods for calibrating the same use internal analog references with negligible time and temperature drifts. A first input reference signal set generated by any accurate, precision analog reference is applied to a data processor. The corresponding output response is compared to the theoretical ideal output response to determine the data processor'"'"'s initial gain and offset errors. This information can be stored in non-volatile memory, recalled, and used to compensate for the data processor'"'"'s initial gain and offset errors during actual use of the data processor. Subsequent errors due to time and temperature drifting can be determined by comparing the output responses to a second input reference signal set which is generated by the internal analog reference. The subsequent errors can be combined with the initial errors to compensate for system errors within the data processor.

Claims

1. A method of calibrating the output of a data processor, comprising the steps of:

applying first and second analog input reference signals I₁ and I₂ from an accurate external reference to generate respective first and second digital output values O₁ and O₂ ;

comparing O₁ and O₂ with respective ideal digital output values O_1t and O_2t to determine initial gain and offset errors A₁ and B₁, respectively, where A₁ =(O₁ -O₂)/(O_1t -O_2t), where B₁ =(O₂ -O_2t)*A₁, and where I₁ and I₂ are selected so that their corresponding respective ideal digital output values O_1t and O_2t are relatively close to the minimum and maximum output values of an analog-to-digital converter circuit within the data processor;

storing A₁ and B₁ in an internal memory storage device;

applying an input signal I_in to the data processor to generate a non-calibrated output signal O_pre-comp ; and

compensating O_pre-comp to thereby output a calibrated signal O_comp to account for initial gain and offset errors A₁ and B₁, where O_comp =(O_pre-comp -B₁)/A₁.

2. The method of claim 1, comprising the further steps of:

applying a third input reference signal I₃ from an internal analog reference to the data processor at approximately the same time errors A₁ and B₁ are determined, to thereby generate a third digital output value O₃ ;

storing O₃ in the memory storage device;

applying a fourth input reference signal I₄ from the internal analog reference just prior to applying I_in, to thereby generate a fourth digital output value O₄, where I₃ is substantially equal to I₄ ;

recalling O₃ from the memory storage device;

comparing O₃ with O₄ to determine a subsequent drift error B₂ in the data processor between the time I₃ and I₄ are respectively applied, where B₂ =O₄ -O₃ ; and

compensating O_pre-comp to account for subsequent drift terror B₂ in addition to initial gain and offset errors A₁ and B₁, to thereby output a calibrated signal O_comp2, where O_comp2 =(O_pre-comp -B₁)/A₁.