Expandable flash-memory mass-storage using shared buddy lines and intermediate flash-bus between device-specific buffers and flash-intelligent DMA controllers
First Claim
1. An expandable flash-memory system comprising:
- a host interface for receiving requests for access of flash memory;
a flash-specific direct-memory access (DMA) controller, responsive to the requests from the host interface, for controlling access of the flash memory, the flash-specific DMA controller generating a sequence of command bytes followed by address bytes to initiate a data transfer from the flash memory;
a flash bus, coupled to the flash-specific DMA controller, the flash bus having shared lines, the shared lines for transmitting the sequence of command bytes and address bytes from the flash-specific DMA controller, the shared lines also transmitting data bytes from the flash-specific DMA controller for storage in the flash-memory system;
flash buffer chips, coupled to the flash bus, for generating control signals for controlling flash-memory chips, the flash buffer chips passing the sequence of command bytes and address bytes from the flash-specific DMA controller to the flash memory;
a plurality of flash-memory chips, the flash-memory chips arranged in banks sharing some of the control signals from a flash buffer chip, the flash-memory chips being non-volatile semiconductor-memory chips that retain data when power is no longer applied;
wherein the flash bus accepts additional flash-memory chips attached through the flash buffer chips for expanding a storage capacity of the expandable flash-memory system,whereby the flash-memory chips are buffered by the flash buffer chips to the flash bus and the flash-specific DMA controller.
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Accused Products
Abstract
A flash-memory system is expandable. Rather than directly connecting individual flash-memory chips to a controller, flash buffer chips are used. Each flash buffer chip can connect to four banks of flash-memory chips. Chip enables for individual chips in a bank are generated from an address sent to the flash buffer chips. Two flash-specific DMA controllers are provided, each with four DMA state machines for controlling the four banks of flash-memory chips attached to a flash buffer chip. This allows for four-way interleaving. Two flash buses connect the two DMA controllers to flash buffer chips. The flash bus has a narrow byte-wide interface to send command, address, and data bytes from the DMA controller to the flash buffer chips. These command, address, and data bytes are then passed through the flash buffer chip to the flash-memory chips. Two additional command signals on the flash bus are used to select and control the flash buffer chips. Busy signals from all flash-memory chips in a bank are connected together, and the four busy signals from the four banks are time-multiplexed to a single common busy line for the flash bus. The four DMA state machines each monitor one period of the busy line, allowing four flash operations to be monitored at a time, even though only one data transfer can occur across the flash bus.
279 Citations
24 Claims
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1. An expandable flash-memory system comprising:
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a host interface for receiving requests for access of flash memory; a flash-specific direct-memory access (DMA) controller, responsive to the requests from the host interface, for controlling access of the flash memory, the flash-specific DMA controller generating a sequence of command bytes followed by address bytes to initiate a data transfer from the flash memory; a flash bus, coupled to the flash-specific DMA controller, the flash bus having shared lines, the shared lines for transmitting the sequence of command bytes and address bytes from the flash-specific DMA controller, the shared lines also transmitting data bytes from the flash-specific DMA controller for storage in the flash-memory system; flash buffer chips, coupled to the flash bus, for generating control signals for controlling flash-memory chips, the flash buffer chips passing the sequence of command bytes and address bytes from the flash-specific DMA controller to the flash memory; a plurality of flash-memory chips, the flash-memory chips arranged in banks sharing some of the control signals from a flash buffer chip, the flash-memory chips being non-volatile semiconductor-memory chips that retain data when power is no longer applied; wherein the flash bus accepts additional flash-memory chips attached through the flash buffer chips for expanding a storage capacity of the expandable flash-memory system, whereby the flash-memory chips are buffered by the flash buffer chips to the flash bus and the flash-specific DMA controller. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A flash-memory storage peripheral comprising:
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a host interface to a host system; a local processor for controlling the flash-memory storage peripheral; a read-only memory (ROM), coupled to the local processor, for storing routines for execution by the local processor, the routines including wear-leveling routines for re-mapping data from over-used or faulty memory blocks to under-used or unused memory blocks; a cache, coupled to the local processor, for temporarily storing data from the host in volatile memory that loses data when power is disconnected; a first flash-specific DMA controller, coupled to the local processor, for generating command, address, and data sequences to a first flash-memory chip in a format required by the first flash-memory chip; a first flash bus, coupled to the first flash-specific DMA controller, for transferring data, address, and commands over shared address/data/command lines; a first flash buffer chip, coupled to the first flash bus, for sending the data, address, and commands from the shared lines of the first flash bus to the first flash-memory chip; a plurality of other flash-memory chips, arranged into banks, the flash-memory chips being non-volatile semiconductor memory chips that retain data when power is lost; other flash buffer chips coupled to the first flash bus, each flash buffer chip coupled to a different plurality of banks of the flash-memory chips; a second flash-specific DMA controller, coupled to the local processor, for generating command, address, and data sequences to a second flash-memory chip in a format required by the second flash-memory chip; a second flash bus, coupled to the second flash-specific DMA controller, for transferring the data, address, and commands over shared address/data/command lines; a second flash buffer chip, coupled to the second flash bus, for sending the data, address, and commands from the shared lines of the second flash bus to the second flash-memory chip; other flash buffer chips coupled to the second flash bus, each flash buffer chip coupled to a different plurality of banks of the flash-memory chips, whereby two flash-specific DMA controllers control access of flash-memory chips through flash buffer chips connected by two flash buses. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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18. A flash storage system comprising:
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a flash-specific direct-memory access (DMA) controller having a DMA state machine for each interleave of a flash memory, the flash memory being organized into an interleave number of interleaves for parallel access; a flash bus having a narrow interface; a bus state machine for driving command, address, and data bytes onto the flash bus in response to one of the DMA state machines; banks of flash-memory chips, the flash-memory chips being non-volatile electrically-erasable-programmable read-only-memory EEPROM integrated circuits, the flash-memory chips being organized as pages of at least 512 bytes, and further organized into blocks of at least 16 pages, the flash-memory chips allowing no less than a page to be read or written and no less than a block to be erased; and flash buffer chips connected to the flash bus, each flash buffer chip connected to a number of banks of the flash-memory chips equal to the interleave number, the flash buffer chips including a decoder for generating a plurality of chip enables for the flash-memory chips connected to the flash buffer chip, the decoder activating one of the chip enables in response to a select code from the DMA state machine; wherein the flash buffer chips pass the command, address, and data bytes from the flash bus through to the flash-memory chips, whereby the flash-specific DMA controller controls a large number of the flash-memory chips through the flash bus and the flash buffer chips. - View Dependent Claims (19, 20)
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21. A flash-memory system comprising:
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a host interface for receiving requests for access of flash memory; a flash-specific direct-memory access (DMA) controller, responsive to the requests from the host interface, for controlling access of the flash memory, the flash-specific DMA controller generating a sequence of command bytes and address bytes to initiate a data transfer from the flash memory; a flash bus, coupled to the flash-specific DMA controller, the flash bus having shared lines, the shared lines for transmitting the sequence of command bytes and address bytes from the flash-specific DMA controller, the shared lines also transmitting data bytes from the flash-specific DMA controller for storage in the flash-memory system; a plurality of flash-memory chips, the flash-memory chips arranged in banks sharing one or more control signals, each flash-memory chip outputting a busy signal to indicate when a flash operation is in progress within the flash-memory chip, wherein all of the busy signals from the flash-memory chips in a bank are connected to a common bank-busy line; wherein the flash-specific DMA controller includes a busy-detector to monitor the common bank-busy line to determine when the flash operation is in progress in the flash-memory chip, whereby the flash-specific DMA controller provides the sequence of command bytes and address bytes onto the shared lines of the flash bus that also transmit the data bytes, the flash-specific DMA also monitoring progress of the flash operation using the common bank-busy line. - View Dependent Claims (22, 23, 24)
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Specification