Multi-tasking sequencer for a TDMA burst mode controller

• US 5,822,308 A
• Filed: 03/21/1996
• Issued: 10/13/1998
• Est. Priority Date: 07/17/1995
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Weigand, David L., Malek, Charles J.
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): Phillips, Matthew C.
• Application Number:
  US08/621,266
• Time in Patent Office: 936 Days
• Field of Search: 370/280, 370/294, 370/336, 370/337, 370/345, 370/347, 370/442, 370/458, 370/498, 370/915
• US Class Current: 370/280
• CPC Class Codes: H04B 7/2643 using time-division multiple access [TDMA] H04B7/2615, H04B7/2618 take precedence
• CPC Class Codes: H04L 7/046 using a dotting sequence
• CPC Class Codes: H04L 7/08 the synchronisation signals recurring cyclically
• CPC Class Codes: H04L 7/10 Arrangements for initial synchronisation

Abstract

A multi-tasking, dynamically controlled micro-sequencer for use in a TDMA communication system is described. Rather than the output of the sequencer being solely a linear sequence of instructions in a microcode RAM, the output of the sequencer is augmented by an output of finite state machines (FSMs) providing a sequence of control codes. The FSMs provide control signals for building a slot in accordance with a specific protocol. The sequencer core provides enabling signals to the FSMs to enable the proper FSM depending upon the mode of the transceiver. A conditional logic block is included in the sequencer core which detects special operation codes (opcodes) for each slot to cause the microcode sequence to jump to a certain routine if a condition is met or not met.

Claims

1. A system for use in TDMA communication network, said network transmitting and receiving bursts of data within time slots, said data in a slot being arranged in accordance with one or more protocols, said system including a sequencer comprising:

a microcode memory;

a logic device connected to an output of said microcode memory; and

one or more state machines for generating control sequences, predetermined by said one or more state machines, in accordance with said protocols, said one or more of said state machines being selectively enabled by said logic device.

2. The system of claim 1 wherein said microcode memory is programmed to contain instructions, said sequencer further comprising:

an address generation unit for generating a series of addresses for addressing said instructions within said microcode memory.

3. The system of claim 2 wherein a particular address generated by said address generation unit causes said microcode memory to output an instruction which, in turn, causes a particular one of said one or more state machines to be enabled for generating a particular control sequence.

4. The system of claim 2 further comprising a conditional logic circuit connected to receive signals from said microcode memory and also connected to receive an operations code, said conditional logic circuit for outputting to said address generation unit an address based on said signals from said microcode memory and said operations code.

5. The system of claim 4 further comprising:

an operations code memory for storing an operations code for one or more of said slots; and

an operations code fetch circuit for conveying a selected operations code to said conditional logic circuit, said conditional logic circuit causing said microcode memory to proceed to a selected address in said microcode memory based on a fetched operations code.

6. The system of claim 1 wherein said one or more state machines comprises:

a first state machine for generating a first control sequence in accordance with a protocol for transmitting data in a particular time slot; and

a second state machine for generating a second control sequence in accordance with a protocol for receiving data in a particular time slot.

7. The system of claim 1 further comprising a combiner connected to an output of said microcode memory and to an output of said one or more state machines.

8. The system of claim 1 wherein an output terminal of said sequencer is connected to a bus.

9. The system of claim 8 further comprising one or more storage devices connected to said bus, said one or more storage devices for receiving said control sequences generated by said one or more state machines and, in response, writing stored data onto said bus.

10. The system of claim 8 further comprising one or more storage devices connected to said bus, said one or more storage devices for receiving said control sequences generated by said one or more state machines and, in response, receiving data from said bus.

11. The system of claim 1 wherein said one or more state machines comprises at least two state machines and wherein said protocols require the formation of a slot having predetermined fields.

12. The system of claim 11 wherein said predetermined fields include a preamble field and a data field.

13. The system of claim 1 wherein said protocols are those used in the personal handy phone system whose requirements are described in RCR standard-28.

14. A method for controlling a TDMA communication system, said system transmitting and receiving bursts of data within time slots, said data in a slot being arranged in accordance with one or more protocols, said method comprising the steps of:

enabling one of a plurality of state machines to generate a predetermined control sequence, said control sequence for creating one of said protocols by selectively enabling devices at various times; and

addressing a microcode memory for generating one or more instructions for determining which of said state machines is to be enabled for carrying out a particular one of said protocols.

15. The method of claim 14 wherein said state machines include a first state machine for creating a slot for transmitting data by said TDMA communication system, and a second state machine for creating a slot for receiving data by said TDMA communication system.

16. The method of claim 14 wherein said state machines are hard-wired to output said predetermined control sequence, said protocols having predetermined fields within a slot, said fields including a preamble field and a data field.