System for inserting instructions into processor instruction stream in order to perform interrupt processing

• US 5,822,578 A
• Filed: 06/05/1995
• Issued: 10/13/1998
• Est. Priority Date: 12/22/1987
• Status: Expired due to Term

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Frank, Steven, Weber, Frederick D., Epstein, David I., Roskosz, John A., Byers, Brett D., Schnorr, Peter C., Lee, Linda Q., Burkhardt, Henry III
• Primary Examiner(s): Ellis, Richard L.
• Application Number:
  US08/461,166
• Time in Patent Office: 1,226 Days
• Field of Search: 395/375, 395/800, 395/741, 395/742, 395/591
• US Class Current: 712/244
• CPC Class Codes: G06F 11/004 Error avoidance G06F11/07 and subgroups take precedence
• CPC Class Codes: G06F 11/0724 in a multiprocessor or a multi-core unit multiprocessors per se G06F15/80
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0772 Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 12/126 with special data handling, e.g. priority of data or instructions, handling errors or pinning
• CPC Class Codes: G06F 2212/272 Cache only memory architecture [COMA]
• CPC Class Codes: G06F 9/3005 to perform operations for flow control
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3842 Speculative instruction execution
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3854 Instruction completion, e.g. retiring, committing or graduating
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3865 using deferred exception handling, e.g. exception flags
• CPC Class Codes: G06F 9/468 Specific access rights for resources, e.g. using capability register
• CPC Class Codes: G06F 9/5016 the resource being the memory
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores
• CPC Class Codes: H04L 12/4637 Interconnected ring systems
• CPC Class Codes: H04L 45/04 : Interdomain routing, e.g. hierarchical routing

Abstract

Digital multiprocessor methods and apparatus comprise a plurality of processors, including a first processor for normally processing an instruction stream including instructions from a first instruction source. At least one of the processors can transmit inserted-instructions to the first processor. Inserted-instructions are executed by the first processor in the same manner as, and without affecting the sequence of, instructions from the first instruction source. The first instruction source can be a memory element, including an instruction cache element for storing digital values representative of instructions and program steps, or an execution unit (CEU) which asserts signals to the instruction cache element to cause instructions to be transmitted to the CEU. The processors include input/output (I/O) processors having direct memory access (DMA) insert elements, which respond to a peripheral device to generate DMA inserted-instructions. These DMA inserted-instructions are executable by the first processing element in the same manner as, and without affecting processing sequence of, the instructions from the first instruction source.

Claims

1. Digital processing apparatus comprising

A. a first instruction source for

storing a plurality of instructions, each associated with a logical program count (PC), and for

responding to a sequence of instruction fetch signals, each designating a PC associated with a requested instruction, for generating an instruction stream including a corresponding sequence of requested instructions,

B. a set of interconnected processing elements, said set of processing elements including a first processing element coupled to said first instruction source for normally processing an instruction stream received therefrom,

said first processing element including pipeline processing means for processing plural instructions substantially concurrently with one another, said pipeline processing means including

fetch means for generating and applying to said first instruction source an instruction fetch signal designating a logical program count (PC) associated with a requested instruction,

execution means for executing, substantially concurrently with generation and application of such instruction fetch signal, a previously received instruction,

C. at least one other of said processing elements including

insert means for generating one or more inserted-instructions and for applying those inserted-instructions to said first processing element to be processed thereby,

D. said execution means including means for processing said inserted-instructions in the same manner as instructions received by the first processing element from the first instruction source, and without affecting the generation and application of a sequence of instruction fetch signals by said fetch means

E. said first processing element further including launch quash means, coupled with said execution means, for selectively preventing processing of an instruction received from said first instruction source in response to a prior instruction fetch signal,

result quash means for selectively limiting a result of processing by said execution means of any of (i) an inserted-instruction received by said first processing element from said at least one other processing element and (ii) an instruction received from said first instruction source in response to a prior instruction fetch signal.

2. Apparatus according to claim 1, further comprising

instruction pipeline means for interconnecting said processing elements and said first instructions source for carrying said instructions, and

wherein said insert means includes means for applying one or more of said inserted-instructions to said instruction pipeline means.

3. Apparatus according to claim 1, wherein said inserted-instructions have the same format as the instructions from the first instruction source.

4. Apparatus according to claim 3, wherein said format includes a selected number of digital instruction bits, wherein at least a first set of said instruction bits form a first instruction field.

5. Apparatus according to claim 3, wherein said format includes a first set of digital instruction bits for specifying selected address signals, and a second set of digital instruction bits, for specifying selected command signals.

6. Apparatus according to claim 1, wherein said first instruction source includes a memory element.

7. Apparatus according to claim 6, wherein said memory element includes an instruction cache element for storing digital values representative of instructions.

8. Apparatus according to claim 7, wherein

said first processing element includes an execution unit (CEU), said CEU including

means for asserting signals to said instruction cache element to cause instructions to be transmitted from said instruction cache element to said CEU.

9. Apparatus according to claim 7, wherein said instructions include cache management instructions inserted by said instruction cache element.

10. Apparatus according to claim 7, wherein said instruction cache element includes means for storing instructions representative of program steps.

15. Apparatus according to claim 1 or 11, wherein

at least a selected one of said processing elements includes at least a first register element associated with that processing element for storing digital values representative of data, and

said insert means includes means for generating and applying to that selected processing element instructions to control movement of data into and out of at least said first register element.

16. Apparatus according to claim 1 or 11, wherein

at least a selected one of said processing elements includes at least a first register element associated with that processing element for storing digital values representative of data, and

said insert means includes means for generating and applying to that selected processing element instructions to cause execution of selected logical operations on selected digital values stored in at least said first register element.

17. Apparatus according to claim 1 or 11, wherein

at least one of said processing elements includes trap means, responsive to a trap signal, for initiating a trap sequence, said trap sequence including selected program steps to be executed in response to a trap signal, and

said insert means includes means for generating and applying to that processing element instructions for generating a trap signal.

18. Apparatus according to claim 1 or 11, wherein

at least one of said processing elements includes

interrupt means, responsive to an interrupt signal, for initiating an interrupt sequence, said interrupt sequence including selected program steps to be executed in response to an interrupt signal, and

said insert means includes means for generating and applying to that processing element instructions for initiating an interrupt sequence.

19. Apparatus according to claim 18, wherein said interrupt means includes means for generating a trap signal in response to an interrupt signal.

11. Digital processing apparatus comprising

A. a first instruction source for responding to a sequence of instruction fetch signals, each designating a logical program count (PC) associated with a requested instruction, for generating an instruction stream including a corresponding sequence of requested instructions,

B. a set of interconnected processing elements, said set of processing elements including a first processing element coupled to said first instruction source for normally processing an instruction stream received therefrom,

said first processing element including pipeline processing means for processing plural instructions substantially concurrently with one another, said pipeline processing means including

fetch means for signal generating and applying to said first instruction source an instruction fetch signal designating a logical program count (PC) associated with a requested instruction,

execution means for executing, substantially concurrently with generation and application of such instruction fetch signal, a previously received instruction,

C. at least one other of said processing elements including input/output processing means for processing signals received from, and transmitted to, a peripheral device,

said input/output processing means including insert means for responding to selected signals from said peripheral device to generate direct memory access (DMA) control instructions and for applying those DMA control instructions to said first processing element to be processed thereby to at least initiate DMA transfers with said peripheral device,

D. said execution means including means for processing said DMA control instructions in the same manner as instructions received by the first processing element from the first instruction source, and without affecting the generation and application of a sequence of instruction fetch signals by said fetch means,

E. said first processing element further including

launch quash means, coupled with said execution means, for selectively preventing processing of an instruction received from said first instruction resource in response to a prior instruction fetch signal,

result quash means for selectively limiting a result of processing by said execution means of any of (i) a DMA control instruction received by said first processing element from said input/output processing means and (ii) an instruction received from said first instruction resource in response to a prior instruction fetch signal.

12. Apparatus according to claim 11, wherein said input/output processing means includes a peripheral interface unit (XIU) for controlling signals received from, and transmitted by, a peripheral device.

13. Apparatus according to claim 11, wherein said input/output processing means includes graphics controller means for controlling signals transmitted to a display device.

14. Apparatus according to claim 11, wherein said input/output processing means includes text searching means for searching data structures representative of text.

20. A method of operating a digital data processor of the type having

a first processing element coupled, along an instruction pipeline, to a first instruction source, wherein said first instruction source

stores a plurality of instructions, each associated with a logical program count (PC), and

responds to a sequence of instruction fetch signals, each designating a PC associated with a requested instruction, for generating and applying to said instruction pipeline an instruction stream including a corresponding sequence of said requested instructions,

said method comprising the steps of

processing, with said first processing element, plural instructions substantially concurrently with one another said processing step including

generating and applying to said first instruction source, with said first processing element, an instruction fetch signal designating a logical program count (PC) associated with a requested instruction,

executing, substantially concurrently with generation and application of such instruction fetch signal, a previously received instruction,

generating, with a second processing element one or more inserted-instructions to be processed by the first processing element, and applying those inserted-instructions to said instruction pipeline,

processing, with said first processing element and without affecting the sequence of instruction fetch signals generated thereby, said inserted-instructions in the same manner as the instruction stream transferred to said first processing element by said first instruction source along said instruction pipeline,

selectively preventing processing of an instruction received from said first instruction resource in response to a prior instruction fetch signal,

selectively limiting a result of processing by said execution means of any of (i) an inserted-instruction received by said first processing element from said at least one other processing element and (ii) an instruction received from said first instruction resource in response to a prior instruction fetch signal.

21. A method of operating a digital data processor of the type having

a first processing element coupled, along an instruction pipeline, to a first instruction source, wherein said first instruction source

stores a plurality of instructions, each associated with a logical program count (PC), and

responds to a sequence of instruction fetch signals, each designating a PC associated with a requested instruction, for generating and applying to said instruction pipeline an instruction stream including a corresponding sequence of said requested instructions,

said method comprising the steps of

processing, with said first processing element, plural instructions substantially concurrently with one another, said processing step including

generating and applying to said first instruction source, with said first processing element, an instruction fetch signal designating a logical program count (PC) associated with a requested instruction,

executing, substantially concurrently with generation and application of such instruction fetch signal, a previously received instruction,

generating, with input/output controller, one or more DMA control instructions for at least initiating DMA transfers with said peripheral device, and applying those DMA control instructions to said instruction pipeline,

processing, with said first processing element and without affecting the sequence of instruction fetch signals generated thereby, said DMA control instructions in the same manner as the instruction stream transferred to said first processing element by said first instruction source along said instruction pipeline

selectively preventing processing of an instruction received from said first instruction resource in response to a prior instruction fetch signal, selectively limiting a result of processing by said execution means of any of (i) a DMA control instruction received by said first processing element from said input/output controller and (ii) an instruction received from said first instruction resource in response to a prior instruction fetch signal.