High bandwidth media processor interface for transmitting data in the form of packets with requests linked to associated responses by identification data

• US 5,822,603 A
• Filed: 11/22/1996
• Issued: 10/13/1998
• Est. Priority Date: 08/16/1995
• Status: Expired due to Term

• Current Assignee: Microunity Systems Engineering Incorporated
• Original Assignee: Microunity Systems Engineering Incorporated
• Inventors: Moussouris, John, Hansen, Craig
• Primary Examiner(s): SHAH, ALPESH
• Application Number:
  US08/754,827
• Time in Patent Office: 690 Days
• Field of Search: 395/800.01, 395/670, 395/376, 395/280, 395/200, 395/200.68, 395/200.8, 364/131-134, 364/736, 364/741, 364/745, 364/754, 364/761, 364/768, 364/736.01, 364/741.05, 364/748.01, 364/754.01
• US Class Current: 712/210
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 15/7832 on one IC chip (single chip microprocessors)
• CPC Class Codes: G06F 15/7842 on one IC chip (single chip microcontrollers)
• CPC Class Codes: G06F 2212/2515 being configurable for different purposes, e.g. as cache or non-cache memory
• CPC Class Codes: G06F 9/30 Arrangements for executing machine instructions, e.g. instruction decode for executing microinstructions G06F9/22
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/30025 Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30038 using a mask
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/3869 Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
• CPC Class Codes: H04N 21/2365 : Multiplexing of several video streams
• CPC Class Codes: H04N 21/238 : Interfacing the downstream path of the transmission network, e.g. adapting the transmission rate of a video stream to network bandwidth; Processing of multiplex streams hybrid fiber coaxial [HFC] networks for downstream channel allocation for video distribution H04L12/2801; flow control in packet networks H04L47/10; real-time communication protocols in data switching networks H04L65/00; scheduling or organising the servicing of application requests H04L67/60
• CPC Class Codes: H04N 21/23805 : Controlling the feeding rate to the network, e.g. by controlling the video pump
• CPC Class Codes: H04N 21/4347 : Demultiplexing of several video streams
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A general purpose, programmable media processor for processing and transmitting a media data stream of audio, video, radio, graphics, encryption, authentication, and networking information in real-time. The media processor incorporates an execution unit that maintains substantially peak data throughout of media data streams. The execution unit includes a dynamically partionable multi-precision arithmetic unit, programmable switch and programmable extended mathematical element. A high bandwidth external interface supplies media data streams at substantially peak rates to a general purpose register file and the multi-precision execution unit. A memory management unit, and instruction and data cache/buffers are also provided. High bandwidth memory controllers are linked in series to provide a memory channel to the general purpose, programmable media processor. The general purpose, programmable media processor is disposed in a network fabric consisting of fiber optic cable, coaxial cable and twisted pair wires to transmit, process and receive single or unified media data streams. Parallel general purpose media processors are disposed throughout the network in a distributed virtual manner to allow for multi-processor operations and sharing of resources through the network. A method for receiving, processing and transmitting media data streams over the communications fabric is also provided.

Claims

1. A high bandwidth processor interface for receiving and transmitting a media stream, comprising:

a data path, the data path operable to transmit and receive media information comprising memory access requests and memory access responses at sustained peak rates;

a plurality of controllers coupled to the data path, the plurality of controllers for controlling the transmission and receipt of the media information to and from the data path; and

a cache coupled to the plurality of controllers and to the data path, for buffering multiple memory access requests and memory access responses, the cache being configured to transmit and receive the media information in the form of packets comprising command information, address information, and data, the command information including identification data for linking the memory access responses to respective memory access requests.

2. The high bandwidth processor interface defined in claim 1, further comprising a high bandwidth data channel for transmitting and receiving the media stream.

3. The high bandwidth processor interface defined in claim 2, wherein the high bandwidth data channel is uni-directional.

4. The high bandwidth processor interface defined in claim 1, further comprising a general purpose programmable media processor coupled to the data path to receive, process and transmit the media information at substantially peak rates.

5. The high bandwidth processor interface defined in claim 1, wherein the peak rate of operation comprises at least one gigabyte of information per second from point to point.

6. The high bandwidth processor interface defined in claim 2, wherein the high bandwidth data channel comprises unidirectional ports having differential data inputs and outputs and a differential clock signal for transmitting and receiving plural bits of data comprising the media stream.

7. The high bandwidth processor interface defined in claim 6, wherein the high bandwidth data channel further comprises a digital skew calibrator to adjust the plural bits of data relative to the differential clock signal to eliminate skew between the data.

8. The high bandwidth processor interface defined in claim 6, wherein the high bandwidth data channel further comprises a phase locked loop to eliminate jitter in the differential clock signal.

9. The high bandwidth processor interface defined in claim 6, wherein the plural bits comprise eight input bits and eight output bits.

10. The high bandwidth processor interface defined in claim 6, wherein the high bandwidth data channel further comprises termination resistors to form matched impedances for each of the plural bits of data.

11. The high bandwidth processor interface defined in claim 2, wherein the high bandwidth data channel comprises plural parallel high bandwidth data channels.