DSP having a plurality of like processors controlled in parallel by an instruction word, and a control processor also controlled by the instruction word

• US 5,822,606 A
• Filed: 02/16/1996
• Issued: 10/13/1998
• Est. Priority Date: 01/11/1996
• Status: Expired due to Term

• Current Assignee: Cufer Asset Ltd LLC (Intellectual Ventures LLC)
• Original Assignee: Steven G. Morton
• Inventors: Morton, Steven G.
• Primary Examiner(s): AN, MENG AI T
• Application Number:
  US08/602,220
• Time in Patent Office: 970 Days
• Field of Search: 395/800.01, 395/800.02, 395/800.07, 395/800.09, 395/800.1, 395/800.15, 395/800.16, 395/800.17, 395/800.2, 395/800.21, 395/800.22 , 395/800.23, 395/800.24, 395/800.28, 395/800.3, 395/379, 395/382, 395/383, 395/390, 395/391, 395/562, 395/563, 395/800.26
• US Class Current: 712/16
• CPC Class Codes: G06F 12/0859 with reload from main memory
• CPC Class Codes: G06F 15/8092 Array of vector units
• CPC Class Codes: G06F 8/45 Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30127 Register windows
• CPC Class Codes: G06F 9/30141 Implementation provisions of register files, e.g. ports
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]

Abstract

The Parallel DSP Chip has a general purpose, reduced instruction set for parallel digital signal processing. The following pertains to the preferred embodiment. Most instruction words are 32 bits long and execute at the rate of one per clock cycle. Each instruction word is executed by a single, pipelined instruction unit that controls the operation of four, 16-bit vector processors in parallel with one group of bits, and the operation of a 24-bit scalar processor with another group of bits. Thus five instructions are typically executed for every instruction word as a result of the parallel architecture. A single, linear, 16 MB, memory address space is used, simplifying program development. The storage of 8- and 16-bit operands for use by the vector processors is supported to maximize memory utilization. The Parallel DSP Chip is specifically designed to support an enhanced C compiler and has two software stack pointers, one for the vector processors and one for the scalar processor, plus an interrupt stack pointer. The Parallel DSP Chip executes a single task in parallel. Using an enhanced C compiler, simple, familiar, scalar processing programming techniques can be used, and a simple, single-task operating system can be used for software development. The basic programming concept is to define one or more arrays of four-element structures using the enhanced C compiler. One element in such a structure is provided for each of the four vector processors. The structure to be processed at any one time is selected by an address computed by the scalar processor. The same operation is applied to all of the elements of the structure by the simultaneous operation of the vector processors. To access the next structure in an array of structures, the scalar processor advances the address by the number of bytes in the structure.

Claims

1. A method for operating a digital data processor, comprising the steps of:

accessing a first instruction from a memory that is coupled to a digital data processor, the digital data processor comprising a first processing element and a plurality of second processing elements, the first instruction being comprised of a plurality of fields;

applying the accessed first instruction to the digital data processor;

controlling an operation of the first processing element of the digital data processor with m first fields of the accessed instruction, where m is a positive integer that is greater than or equal to one; and

simultaneously controlling an operation of each of the plurality of second processing elements of the digital data processor with n second fields of the accessed instruction, where n is greater than or equal to one, said n second fields providing identical control to the plurality of second processing elements;

wherein each of the first processing element and the plurality of second processing elements is comprised of an addressable register bank for storing operands, wherein each of the first processing element and the plurality of second processing elements is comprised of logic means for performing an operation on operands read out from an associated one of the register banks, wherein the m first fields of the instruction control the first processing element by specifying a first register within the register bank, a second register within the register bank, and an operation to be performed by the logic means on operands read out from the specified first and second registers, and wherein the n second fields of the instruction control each of the plurality of second processing elements by specifying, for each of the plurality of second processing elements, a first register within the register bank, a second register within the register bank, and an operation to be performed by the logic means on operands read out from the specified first and second registers.

2. A method as set forth in claim 1, wherein m and n are both equal to three.

3. A method as set forth in claim 1, wherein the logic means of the first processing element is comprised of an arithmetic logic unit (ALU) for performing a specified operation on at least one operand read out from the specified first and second registers, and wherein the logic means of each of the plurality of second processing elements is comprised of an ALU and a multiplier/accumulator for performing a specified operation on at least one operand read out from the specified first and second registers.

4. A method as set forth in claim 3, wherein the specified operation is executed at a rate of one per clock cycle.

5. A digital signal processor, comprising:

a first processing element comprised of a first addressable register bank for storing operands and first logic means for performing an operation on at least one operand read out from said first register bank;

a plurality of second processing elements each of which is comprised of a second addressable register bank for storing operands and second logic means for performing an operation on at least one operand read out from said second register bank; and

each of said first processing element and said plurality of second processing elements being controlled in parallel by an instruction, said instruction comprising a first field for specifying a first register within said first register bank, a second field for specifying a second register within said first register bank, a third field for specifying an operation to be performed by said first logic means on operands read out from at least one of said specified first and second registers of said first register bank, a fourth field for specifying in parallel a first register within each of said second register banks, a fifth field for specifying in parallel a second register within each of said second register banks, and a sixth field for specifying in parallel an operation to be performed by each of said second logic means on at least one operand read out from an associated one of said specified first and second registers of said associated one of said second register banks.

6. A digital signal processor circuit as set forth in claim 5, wherein said first logic means is comprised of an arithmetic logic unit (ALU), and wherein said second logic means of each of said plurality of second processing elements is comprised of an ALU and also a multiplier/accumulator.

7. A digital signal processor circuit as set forth in claim 5, wherein said first processing element is bidirectionally coupled to individual ones of said plurality of second processing elements through a crossbar switch and a data cache.

8. A digital signal processor circuit as set forth in claim 5, wherein individual ones of said plurality of second processing elements are bidirectionally coupled to through a crossbar switch to a data cache storing data words of m-bits, and wherein individual ones of said second processing elements simultaneously operate on a subset of said m-bits within a data word.