Method and apparatus for automated wafer level testing and reliability data analysis

• US 5,822,717 A
• Filed: 07/31/1995
• Issued: 10/13/1998
• Est. Priority Date: 07/31/1995
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Tsiang, Jerry, Peng, Yeng-Kaung, Lantz, Mikkel, Shiau, Ying
• Primary Examiner(s): Trammell, James P.
• Application Number:
  US08/509,362
• Time in Patent Office: 1,170 Days
• Field of Search: 364/578, 364/580, 364/579, 364/480-487, 364/551.01, 364/552, 364/554, 364/488-491, 364/468.17, 364/468.28, 438/14-18, 324/765-769, 324/719
• US Class Current: 702/108
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2834 Automated test systems [ATE]; using microprocessors or computers G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736
• CPC Class Codes: G01R 31/2851 Testing of integrated circuits [IC] G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801
• CPC Class Codes: G01R 31/31903 tester configuration

Abstract

Methods and apparatus are disclosed for testing integrated circuits at the wafer level and for integrating test results, calculation of lifetimes and generation of trend charts in a common database following testing. A wafer tester controller is supplemented with additional hardware and software to avoid data transfer errors and facilitate processing and storage of test results. The data base is available over a network to all areas of an organization.

Claims

1. A wafer testing system comprising:

a network;

at least one wafer tester, comprising an automatic test probe and a tester controller, connected to said network;

a database connected to said network receiving test results from the at least one said wafer tester, and

analysis software on the tester controller for processing test results to derive a predicted lifetime for each integrated circuit on a wafer being tested.

2. The wafer testing system of claim 1 in which the tester controller writes the results of a lifetime calculation to the database.

3. The wafer testing system of claim 1 in which the tester controller executes a procedure by which lifetime is determined by:

Collecting breakdown voltages of capacitors at 2 stress conditions,

Sorting breakdown voltages in increasing order and plotting cumulative failure percent versus breakdown voltages for each condition,

Finding breakdown difference (Δ

V) between 2 stress conditions at different failure percents,

Finding beta values at different failure percentages ##EQU3## Finding the smallest value of beta and also breakdown voltage value at 5% failure, and

Calculate lifetime at failure rate of 5%, using;

space="preserve" listing-type="equation">log(t)-log 0.03+β

(BV.sub.5% -X),

where X is the operating voltage of device being tested.

4. A computer readable diskette or memory having stored thereon a computer program for implementing the system of claim 3.

5. The wafer testing system of claim 1 further comprising:

a memory containing program commands for executing a procedure by which lifetime is determined in accordance with the following;

measuring the peak substrate current for a fixed source to drain voltage as a function of scan gate voltage for one of an N or P channel device, and

determining lifetime using;

for N channel devices lifetime=A(Isub)^-N, or

for P channel devices lifetime=A(Igate)^-N.

6. A computer readable diskette or memory having stored thereon a computer program for implementing the system of claim 5.

7. The wafer testing system of claim 1 further comprising:

a plurality of wafer testers connected to the network.

8. A method of automatically testing integrated circuits fabricated on a wafer using a wafer tester comprising:

probing selected points on each integrated circuit of a wafer to measure one or more electrical values;

storing the values with data identifying the integrated circuit and wafer at the wafer tester;

processing the values to produce an estimate of lifetime for the integrated circuit at the wafer tester, and

storing the estimate of lifetime together with the values at a location remote from the wafer tester over a network.

9. A method of determining lifetime of integrated circuit components using a wafer tester, comprising the steps of:

a. Collecting breakdown voltages of capacitors at 2 stress conditions using said wafer tester;

b. Sorting breakdown voltages in increasing order and plotting cumulative failure percent verses breakdown voltages for each condition;

c. Determining breakdown difference voltage between 2 stress conditions at different failure percents,

d. Finding beta values at different failure percentages ##EQU4## e. Finding the smallest value of beta and also breakdown voltage value at 5% failure, and

f. Calculating lifetime at failure rate of 5%, using;

space="preserve" listing-type="equation">log(t)-log 0.03+β

(BV.sub.5% -X),

where X is the operating voltage of device being tested.

10. A method of determining lifetime of integrated circuit components using a wafer tester, comprising the steps of:

a. measuring the peak substrate current for a fixed source to drain voltage as a function of scan gate voltage for one of an N or P channel device, and

determining lifetime using;

for N channel devices lifetime=A(Isub)^-N, or

for P channel devices lifetime=A(Igate)^-N.