Method and apparatus for automated wafer level testing and reliability data analysis
First Claim
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1. A wafer testing system comprising:
- a network;
at least one wafer tester, comprising an automatic test probe and a tester controller, connected to said network;
a database connected to said network receiving test results from the at least one said wafer tester, andanalysis software on the tester controller for processing test results to derive a predicted lifetime for each integrated circuit on a wafer being tested.
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Abstract
Methods and apparatus are disclosed for testing integrated circuits at the wafer level and for integrating test results, calculation of lifetimes and generation of trend charts in a common database following testing. A wafer tester controller is supplemented with additional hardware and software to avoid data transfer errors and facilitate processing and storage of test results. The data base is available over a network to all areas of an organization.
43 Citations
10 Claims
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1. A wafer testing system comprising:
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a network; at least one wafer tester, comprising an automatic test probe and a tester controller, connected to said network; a database connected to said network receiving test results from the at least one said wafer tester, and analysis software on the tester controller for processing test results to derive a predicted lifetime for each integrated circuit on a wafer being tested. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method of automatically testing integrated circuits fabricated on a wafer using a wafer tester comprising:
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probing selected points on each integrated circuit of a wafer to measure one or more electrical values; storing the values with data identifying the integrated circuit and wafer at the wafer tester; processing the values to produce an estimate of lifetime for the integrated circuit at the wafer tester, and storing the estimate of lifetime together with the values at a location remote from the wafer tester over a network.
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9. A method of determining lifetime of integrated circuit components using a wafer tester, comprising the steps of:
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a. Collecting breakdown voltages of capacitors at 2 stress conditions using said wafer tester; b. Sorting breakdown voltages in increasing order and plotting cumulative failure percent verses breakdown voltages for each condition; c. Determining breakdown difference voltage between 2 stress conditions at different failure percents, d. Finding beta values at different failure percentages ##EQU4## e. Finding the smallest value of beta and also breakdown voltage value at 5% failure, and f. Calculating lifetime at failure rate of 5%, using;
space="preserve" listing-type="equation">log(t)-log 0.03+β
(BV.sub.5% -X),where X is the operating voltage of device being tested.
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10. A method of determining lifetime of integrated circuit components using a wafer tester, comprising the steps of:
a. measuring the peak substrate current for a fixed source to drain voltage as a function of scan gate voltage for one of an N or P channel device, and determining lifetime using; for N channel devices lifetime=A(Isub)-N, or for P channel devices lifetime=A(Igate)-N.
Specification