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Dual usage memory selectively behaving as a victim cache for L1 cache or as a tag array for L2 cache

  • US 5,822,755 A
  • Filed: 01/25/1996
  • Issued: 10/13/1998
  • Est. Priority Date: 01/25/1996
  • Status: Expired due to Fees
First Claim
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1. A microprocessor architecture, the microprocessor architecture including a control means capable of providing a control signal the microprocessor architecture having:

  • first cache memory means disposed on a first substrate for storing data;

    first cache tag memory means disposed on the first substrate for storing data pertaining to the contents of the first cache memory means; and

    second memory means disposed on the first substrate for storing data in a first mode of operation and for storing information relating to the contents of a second cache memory means in a second mode of operation, wherein the first and second modes of operation are determined by the control means.

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