Dual usage memory selectively behaving as a victim cache for L1 cache or as a tag array for L2 cache

• US 5,822,755 A
• Filed: 01/25/1996
• Issued: 10/13/1998
• Est. Priority Date: 01/25/1996
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Shippy, David
• Primary Examiner(s): Swann, Tod R.
• Assistant Examiner(s): Lee, Felix B.
• Application Number:
  US08/591,921
• Time in Patent Office: 992 Days
• Field of Search: 395/365, 395/445
• US Class Current: 711/118
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 2212/2515 being configurable for different purposes, e.g. as cache or non-cache memory

Abstract

A microprocessor architecture including a first cache memory disposed on-chip for storing data along with an associated on-chip tag memory. A second memory is provided on-chip for storing data in a first mode of operation and for storing tags relating to the contents of a second cache memory in a second mode of operation. The mode of operation is set by control logic. The mode is selected by setting a bit in a mode control register. When the bit is set, the control logic changes the system from a first mode in which the second memory serves as additional on-chip cache memory to a second mode in which the second memory stores tags for an external level 2 cache memory. The invention provides a flexible cache structure in which increased on-chip cache is provided or tag memory area is provided for an off-chip level 2 cache.

Claims

1. A microprocessor architecture, the microprocessor architecture including a control means capable of providing a control signal the microprocessor architecture having:

first cache memory means disposed on a first substrate for storing data;

first cache tag memory means disposed on the first substrate for storing data pertaining to the contents of the first cache memory means; and

second memory means disposed on the first substrate for storing data in a first mode of operation and for storing information relating to the contents of a second cache memory means in a second mode of operation, wherein the first and second modes of operation are determined by the control means.

2. The invention of claim 1 wherein the first mode of operation comprises a victim cache mode.

3. The invention of claim 1 wherein the second mode of operation comprises a tag store mode.

4. The invention of claim 3 wherein the second cache memory means stores tags for the second cache memory in the tag store mode.

5. The invention of claim 1 wherein the first cache memory means is a level 1 cache memory.

6. The invention of claim 5 wherein the first cache tag memory means is a level 1 cache tag memory.

7. The invention of claim 6 wherein the second cache memory means comprises a level 2 cache memory.

8. The invention of claim 7 wherein the level 2 cache memory is disposed on a second substrate.

9. A microprocessor architecture, the microprocessor architecture including a control means capable of providing a control signal, the microprocessor architecture having:

a level 1 cache memory disposed on a first substrate for storing data;

a level 1 cache tag memory disposed on the first substrate for storing data pertaining to the contents of the level 1 cache memory; and

a second memory disposed on the first substrate for storing data in a first mode of operation and for storing information relating to the contents of a level 2 cache memory in a second mode of operation, wherein the first and second modes of operation are determined by the control means.

10. The invention of claim 9 wherein the second memory acts as a victim cache in the first mode of operation.

11. The invention of claim 9 wherein the second memory acts as tag memory in the second mode of operation.

12. The invention of claim 9 wherein the level 2 cache memory is disposed on a second substrate.