Method and system for high performance dynamic and user programmable cache arbitration

• US 5,822,758 A
• Filed: 09/09/1996
• Issued: 10/13/1998
• Est. Priority Date: 09/09/1996
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Shippy, David J., Olson, Christopher Hans, Elliott, Timothy Alan, Loper, Albert John
• Primary Examiner(s): Swann, Tod R.
• Assistant Examiner(s): Rockett, Esteban A.
• Application Number:
  US08/709,793
• Time in Patent Office: 764 Days
• Field of Search: 711/130, 711/149, 711/150, 711/151
• US Class Current: 711/130
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 13/18 based on priority control G06F13/1605 takes precedence

Abstract

A system and method for improving arbitration of a plurality of events that may require access to a cache is disclosed. In a first aspect, the method and system provide dynamic arbitration. The first aspect comprises first logic for determining whether at least one of the plurality of events requires access to the cache and for outputting at least one signal in response thereto. Second logic coupled to the first logic determines the priority of each of the plurality of events in response to the at least one signal and outputs a second signal specifying the priority of each event. Third logic coupled to the second logic grants access to the cache in response to the second signal. A second aspect of the method and system provides user programmable arbitration. The second aspect comprises a storage unit which allows the user to input information indicating the priority of at least one of the plurality of events and outputs a first signal in response to the information. In the second aspect, first logic coupled to the storage unit determines the priority of each of the plurality of events in response to the first signal and outputs a second signal indicating the priority of each event. Second logic coupled to the first logic grants access to the cache in response to the second signal.

Claims

1. A system for a dynamic arbitration of access by a plurality of events to a cache comprising:

first logic for determining whether at least one of the plurality of events requires access to the cache and for outputting at least one signal in response thereto;

second logic coupled to the first logic for determining the priority of each of the plurality of events in response to the at least one signal and for outputting a second signal specifying the priority of each event; and

third logic coupled to the second logic for granting access to the cache in response to the second signal specifying the priority of each event, the third logic comprising a first tier of a plurality multiplexers such that each multiplexer of the first tier corresponds to a particular priority and provides one of the plurality of events having the particular priority, and a second tier of at least one multiplexer coupled to the first tier, the second tier for granting access to the cache according to the particular priority of each multiplexer of the first tier.

2. The system of claim 1 wherein the first logic further comprises a program manageable special purpose register.

3. The system of claim 2 wherein the second logic further includes a performance monitor evaluation for automatically adjusting the priority of one of the plurality of events in response to a signal output from the program manageable special purpose register.

4. The system of claim 3 wherein the cache is a single ported cache.

5. The system of claim 4 wherein the cache is a level two cache and wherein the plurality of events further comprises events requiring access to a level one cache.

6. The system of claim 1 wherein the first logic further comprises a performance monitor.

7. The system of claim 6 wherein the first logic further comprises a program manageable special purpose register.

8. A system for a user programmable arbitration of access by a plurality of events to a cache comprising:

a logic unit for allowing the user to input information indicating the priority of at least one of the plurality of events and for outputting a first signal in response to the information;

first logic coupled to the logic unit for determining the priority of each of the plurality of events in response to the first signal and for outputting a second signal specifying the priority of each event; and

second logic coupled to the first logic, for granting access to the cache in response to the second signal specifying the priority of each event, the second logic comprising a first tier of a plurality of multiplexers such that each multiplexer of the first tier corresponds to a particular priority and provides one of the plurality of events having the particular priority, and a second tier of at least one multiplexer coupled to the first tier, the second tier for granting access to the cache according to the particular priority of each multiplexer of the first tier.

9. The system of claim 8 wherein the logic unit further comprises a register.

10. The system of claim 8 wherein the information input by the user further comprises at least one bit indicating order of the at least one event and at least a second of the plurality of events.

11. The system of claim 10 wherein the cache is a single ported cache.

12. The system of claim 11 wherein the cache is a level two cache;

and wherein the plurality of events further comprises events requiring access to a level one cache.

13. A system for a dynamic arbitration and a user programmable arbitration of access by a plurality of events to a cache comprising:

a first logic for determining whether at least one of the plurality of events requires access to the cache, and for outputting at least one signal in response thereto;

second logic coupled to the first logic for determining the priority of each of the plurality of events in response to the at least one signal and for outputting a second signal specifying the priority of each event;

a logic unit for allowing the user to input information indicating the priority of at least one of the plurality of events and for outputting a third signal in response to the information;

third logic coupled to the logic unit for determining the priority of each of the plurality of events in response to the third signal and for outputting a fourth signal specifying the priority of each event;

a mode detector coupled with the second logic and the third logic, the mode detector for determining whether dynamic or user programmable arbitration will be performed and for outputting a fifth signal, the fifth signal being in response to the second signal when dynamic arbitration is to be performed, and the fifth signal being in response to the fourth signal when user programmable arbitration is to be performed;

fourth logic coupled to the mode detector, for granting access to the cache in response to the fifth signal.

14. The system of claim 13 wherein the fourth logic further comprises:

a first tier of a plurality of multiplexers, each multiplexer of the first tier corresponding to a particular priority, each multiplexer of the first tier for providing one of the plurality of events having the particular priority; and

a second tier of at least one multiplexer, the second tier coupled to the first tier, the second tier for granting access to the cache according to the particular priority of each multiplexer of the first tier.

15. The system of claim 14 wherein the information input by the user further comprises at least one bit indicating order of the at least one of the plurality of events and at least a second of the plurality of events.

16. The system of claim 15 wherein the first logic further comprises a program manageable register.

17. The system of claim 16 wherein the cache is a single ported cache.

18. The system of claim 17 wherein the cache is a level two cache and wherein the plurality of events further comprises events requiring access to a level one cache.

19. The system of claim 15 wherein the first logic further comprises a performance monitor.

20. The system of claim 19 wherein the first logic further comprises a program manageable special purpose register.

21. A system for a dynamic arbitration of access by a plurality of events to a cache in a computer system including a processor comprising:

first logic for monitoring the processor, for determining whether at least one of the plurality of events requires access to the cache, and for outputting at least one signal in response thereto;

second logic coupled to the first logic for determining the priority of each of the plurality of events in response to the at least one signal and for providing a second signal specifying the priority of each event; and

third logic coupled to the second logic, for granting access to the cache in response to the second signal specifying the priority of each event, the third logic comprising a first tier of a plurality of multiplexers such that each multiplexer of the first tier corresponds to a particular priority and provides one of the plurality of events having the particular priority, and a second tier of at least one multiplexer, the second tier coupled to the first tier, the second tier for granting access to the cache according to the particular priority of each multiplexer of the first tier.

22. The system of claim 21 wherein the first logic further comprises a program manageable special purpose register.

23. The system of claim 22 wherein the second logic further includes a performance monitor evaluation for automatically adjusting the priority of one of the plurality of events in response to a signal output from the program manageable special purpose register.

24. The system of claim 23 wherein the cache is a single ported cache.

25. The system of claim 24 wherein the cache is a level two cache and wherein the plurality of events further comprises events requiring access to a level one cache.

26. A system for a dynamic arbitration and a user programmable arbitration of access by a plurality of events to a cache in a computer system including a processor comprising:

a first logic for determining whether at least one of the plurality of events requires access to the cache, and for outputting at least one signal in response thereto;

second logic coupled to the first logic for determining the priority of each of the plurality of events in response to the at least one signal and for providing a second signal specifying the priority of each event;

a logic unit for allowing the user to input information indicating the priority of at least one of the plurality of events and for providing a third signal in response to the information;

third logic coupled to the logic unit for determining the priority of each of the plurality of events in response to the third signal and for outputting a fourth signal specifying the priority of each event;

a mode detector coupled with the first logic and the third logic, for determining whether dynamic or user programmable arbitration will be performed and for outputting a fifth signal, the fifth signal being in response to the second signal when dynamic arbitration is to be performed, and the fifth signal being in response to the fourth signal when user programmable arbitration is to be performed;

fourth logic coupled to the mode detector, for granting access to the cache in response to the fifth signal.

27. The system of claim 26 wherein the fourth logic further comprises:

a first tier of a plurality of multiplexers, each multiplexer of the first tier corresponding to a particular priority, each multiplexer of the first tier for providing one of the plurality of events having the particular priority; and

a second tier of at least one multiplexer, the second tier coupled to the first tier, the second tier for granting access to the cache according to the particular priority of each multiplexer of the first tier.

28. The system of claim 27 wherein the information input by the user further comprises at least one bit indicating order of the at least one of the plurality of events and at least a second of the plurality of events.

29. The system of claim 28 wherein the first logic further comprises a program manageable register.

30. The system of claim 29 wherein the cache is a single ported cache.

31. The system of claim 30 wherein the cache is a level two cache and wherein the plurality of events further comprises events requiring access to a level one cache.

32. A method for a dynamic arbitration of access by a plurality of events to a cache comprising the steps of:

a) determining whether at least one of the plurality of events requires access to the cache;

b) outputting at least one signal in response to the determination of whether the at least one of the plurality of events requires access to the cache;

c) determining the priority of each of the plurality of events in response to the at least one signal;

d) outputting a second signal specifying the priority of each event; and

e) granting access to the cache in response to the second signal specifying the priority of each event, including providing each of the plurality of events to a first tier of a plurality of multiplexers wherein each multiplexer of the first tier corresponds to a particular priority, outputting a signal comprising one of the plurality of events corresponding to the particular priority from each multiplexer of the first tier to a second tier of at least one multiplexer wherein the second tier of at least one multiplexer is for granting access to the cache, and granting access to the cache according to the particular priority.

33. The method of claim 32 wherein the cache is a single ported cache.

34. The method of claim 33 wherein the cache is a level two cache and wherein the plurality of events further comprises events requiring access to a level one cache.

35. A method for a user programmable arbitration of access by a plurality of events to a cache comprising the steps of:

a) providing information input by the user, the information indicating the priority of at least one of the plurality of events;

b) outputting a first signal in response to the information input by the user;

c) determining the priority of each of the plurality of events in response to the signal;

d) outputting a second signal specifying the priority of each event; and

e) granting access to the cache in response to the second signal specifying the priority of each event, including providing each of the plurality of events to a first tier of a plurality of multiplexers wherein each multiplexer of the first tier corresponds to a particular priority, providing a multiplexer output comprising one of the plurality of events corresponding to the particular priority from each multiplexer of the first tier to a second tier of at least one multiplexer wherein the second tier of at least one multiplexer is for granting access to the cache, and granting access to the cache to the particular priority.

36. The method of claim 35 wherein the information input by the user further comprises at least one bit indicating order of the at least one of the plurality of events and at least a second of the plurality of events.

37. The method of claim 36 wherein the cache is a single ported cache.

38. The method of claim 37 wherein the cache is a level two cache and wherein the plurality of events further comprises events requiring access to a level one cache.

39. A method for a dynamic arbitration and a user programmable arbitration of access by a plurality of events to a cache comprising the steps of:

a) determining whether at least one of the plurality of events requires access to the cache;

b) outputting at least one signal in response to the determination of whether the at least one of the plurality of events requires access to the cache;

c) determining the priority of each of the plurality of events in response to the at least one signal;

d) outputting a second signal indicating the priority of each event;

e) providing information input by the user, the information determining the priority of at least one of the plurality of events;

f) outputting a third signal in response to the information;

g) determining the priority of each of the plurality of events in response to the third signal;

h) outputting a fourth signal indicating the priority of each event;

i) outputting a fifth signal, the fifth signal being in response to the second signal if the dynamic arbitration is to be performed, and the fifth signal being in response to the fourth signal if the user programmable arbitration is to be performed; and

j) granting access to the cache in response to the fifth signal.

40. The method of claim 39 wherein the information input by the user further comprises at least one bit indicating order of the at least one of the plurality of events and at least a second of the plurality of events.

41. The method of claim 40 wherein the cache is a single ported cache.

42. The method of claim 41 wherein the cache is a level two cache and wherein the plurality of events further comprises events requiring access to a level one cache.

43. The method of claim 42 wherein cache access granting step (j) further comprises the steps of:

j1) providing each of the plurality of events to a first tier of a plurality of multiplexers, each multiplexer of the first tier corresponding to a particular priority;

j2) providing a multiplexer output from each multiplexer of the first tier to a second tier of at least one multiplexer, the multiplexer output further comprising a one of the plurality of events corresponding to the particular priority, the second tier for granting access to the cache; and

j3) granting access to the cache according to the cache according to the particular priority of each multiplexer of the first tier of at least one multiplexer.