Method and apparartus for sharing a signal line between agents
First Claim
1. A method for providing cache line status within a system, the method comprising the steps of:
- determining a first cache line status and determining a second cache line status;
a second agent indicating completion of determining the second cache line status;
after determination of the first cache line status by a first agent and determination of the second cache line status, the first agent indicating that the cache line status from the first and second caches is available;
if the first cache line status is that of a hit to a modified line, the first cache indicating the cache line status from the first and second caches is a hit to a modified line; and
if the second cache line status is that of a hit to a modified line, the second cache indicating the cache line status from the first and second caches is a hit to a modified line.
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Accused Products
Abstract
Memory bus extensions to a high speed peripheral bus are presented. Specifically, sideband signals are used to overlay advanced mechanisms for cache attribute mapping, cache consistency cycles, and dual processor support onto a high speed peripheral bus. In the case of cache attribute mapping, three cache memory attribute signals that have been supported in previous processors and caches are replaced by two cache attribute signals that maintain all the functionality of the three original signals. In the case of cache consistency cycles, advanced modes of operation are presented. These include support of fast writes, the discarding of write back data by a cache for full cache line writes, and read intervention that permits a cache to supply data in response to a memory read. In the case of dual processor support, several new signals and an associated protocol for support of dual processors are presented. Specific support falls into three areas: the extension of snooping to support multiple caches, the support of shared data between the two processors, and the provision of a processor and upgrade arbitration protocol that permits dual processors to share a single grant signal line.
70 Citations
11 Claims
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1. A method for providing cache line status within a system, the method comprising the steps of:
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determining a first cache line status and determining a second cache line status; a second agent indicating completion of determining the second cache line status; after determination of the first cache line status by a first agent and determination of the second cache line status, the first agent indicating that the cache line status from the first and second caches is available; if the first cache line status is that of a hit to a modified line, the first cache indicating the cache line status from the first and second caches is a hit to a modified line; and if the second cache line status is that of a hit to a modified line, the second cache indicating the cache line status from the first and second caches is a hit to a modified line. - View Dependent Claims (2)
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3. An apparatus for providing cache line status within a system, the system including a first agent having a first cache and a second agent having a second cache, the apparatus comprising:
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a first means for the second agent to determine a second cache line status within the second cache having a first signal to indicate determination of the second cache line status, the first means configured to drive a second signal to indicate the cache line status from the first and second caches; a second means for the first agent to determine a first cache line status within the first cache, the second means configured to receive the first signal, drive the second signal to indicate the cache line status from the first and second caches, and drive a third signal to indicate that the cache line status from the first and second caches is available after determination of the first cache line status and receiving the first signal, wherein if the first cache line status is that of a hit to a modified line, the first cache asserting the second signal line and if the second cache line status is that of a hit to a modified line, the second cache asserting the second signal line. - View Dependent Claims (4, 5)
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6. An apparatus for providing cache line status within a system, the system including a first agent having a first cache and a second agent having a second cache, the apparatus comprising:
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a first cache line status determiner for the second agent to determine a second cache line status within the second cache, the first cache line status determiner configured to drive a first signal to indicate determination of the first cache line status and a second signal to indicate the cache line status from the first and second caches; a second cache line status determiner for the first agent to determine a first cache line status within the second cache, the second cache line status determiner configured to receive the first signal, drive a third signal to indicate that the cache line status from the first and second caches is available, and drive the second signal to indicate the cache line status from the first and second caches; wherein if the first cache line status is that of a hit to a modified line, the first cache asserting the second signal line and if the second cache line status is that of a hit to a modified line, the second cache asserting the second signal line. - View Dependent Claims (7, 8)
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9. An system comprising:
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a first agent having a first cache; a second agent having a second cache; a first cache line status determiner for the first agent to determine a first cache line status within the first cache, the first cache line status determiner configured to drive a first signal to indicate determination of the first cache line status and a second signal to indicate the cache line status from the first and second caches; and a second cache line status determiner for the second agent to determine a second cache line status within the second cache, the second cache line status determiner configured to receive the first signal, drive a third signal to indicate that the cache line status from the first and second caches is available, and drive the second signal to indicate the cache line status from the first and second caches; wherein if the first cache line status is that of a hit to a modified line, the first cache line status determiner asserting the second signal and if the second cache line status is that of a hit to a modified line, the second cache line status determiner asserting the second signal. - View Dependent Claims (10, 11)
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Specification