Method and apparatus for fabricating self-assembling microstructures

• US 5,824,186 A
• Filed: 06/07/1995
• Issued: 10/20/1998
• Est. Priority Date: 12/17/1993
• Status: Expired due to Term

• Current Assignee: Regents of the University of California (University of California)
• Original Assignee: Regents of the University of California (University of California)
• Inventors: Smith, John Stephen, Yeh, Hsi-Jen J.
• Primary Examiner(s): POWELL, WILLIAM A
• Application Number:
  US08/485,478
• Time in Patent Office: 1,231 Days
• Field of Search: 216/2, 216/18, 216/20, 216/33, 216/39, 156/655.1, 156/657.1, 156/662.1, 156/633.1, 156/297, 156/298, 156/299, 156/649.1, 156/659.11
• US Class Current: 438/597
• CPC Class Codes: G02F 1/136 Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit G02F1/135 takes precedence
• CPC Class Codes: G02F 1/1362 Active matrix addressed cells G02F1/134336, G02F1/134363 take precedence
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 21/02002 Preparing wafers
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 21/7813 leaving a reusable substrate, e.g. epitaxial lift off
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2224/24225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/24227 the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
• CPC Class Codes: H01L 2224/83136 involving guiding structures, e.g. spacers or supporting members
• CPC Class Codes: H01L 2224/8319 Arrangement of the layer connectors prior to mounting
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 2224/95085 being a liquid, e.g. for fluidic self-assembly
• CPC Class Codes: H01L 2224/95092 Atmospheric pressure, e.g. dry self-assembly
• CPC Class Codes: H01L 2224/95122 by applying vibration
• CPC Class Codes: H01L 2224/95136 involving guiding structures, e.g. shape matching, spacers or supporting members
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/26 : Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/95 : at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
• CPC Class Codes: H01L 25/04 : the devices not having separate containers
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0753 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 29/0657 : characterised by the shape of the body
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01061 : Promethium [Pm]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01084 : Polonium [Po]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10158 : at the passive surface
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/10336 : Aluminium gallium arsenide [AlGaAs]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15155 : the shape of the recess being other than a cuboid
• CPC Class Codes: H01L 2924/15157 : Top view
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3512 : Cracking
• CPC Class Codes: H01L 33/20 : with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: H01S 5/0207 : Substrates having a special shape
• CPC Class Codes: H01S 5/0215 : Bonding to the substrate
• CPC Class Codes: H01S 5/0217 : Removal of the substrate
• CPC Class Codes: Y10T 29/49895 : Associating parts by use of aligning means [e.g., use of a drift pin or a "fixture"]

Abstract

A method and apparatus for assembling microstructures onto a substrate through fluid transport. The microstructures being shaped blocks self-align into recessed regions located on a substrate such that the microstructure becomes integral with the substrate. The improved method includes a step of transferring the shaped blocks into a fluid to create a slurry. Such slurry is then dispensed evenly or circulated over the top surface of a substrate having recessed regions thereon. The microstructure via the shape and fluid tumbles onto the surface of the substrate, self-aligns, and engages into a recessed region.

Claims

1. A method of assembling a microstructure on a substrate, said substrate comprising a top surface with at least one recessed region thereon, comprising the steps of:

providing a plurality of shaped blocks in a fluid to form a slurry; and

circulating said slurry over said substrate at a rate where at least one of said shaped blocks is disposed at a selected orientation into said recessed region, each of said shaped blocks comprising a tapered edge to fit into said recessed region at said selected orientation.

2. The method of claim 1 wherein each of said shaped blocks includes at least one electronic device.

3. The method of claim 1 wherein each of said shaped blocks includes a portion of an electronic device.

4. The method of claim 1 wherein said substrate is selected from a group consisting of a silicon wafer, plastic sheet, gallium arsenide wafer, glass substrate, and ceramic substrate.

5. The method of claim 1 wherein said fluid is an inert fluid selected from a group consisting of water, acetone, and alcohol.

6. The method of claim 1 wherein said each of said shaped blocks include a trapezoidal profile.

7. The method of claim 6 wherein each of said recessed regions in said substrate is shaped substantially trapezoidal to complement each of said shaped blocks.

8. The method of claim 1 wherein a gas circulates said slurry over said substrate.

9. The method of claim 8 wherein said gas includes nitrogen.

10. The method of claim 1 wherein each of said blocks comprises a semiconductor material.

11. The method of claim 1 wherein each of said blocks comprises a truncated pyramid shape, said truncated pyramid shape including a base and sides protruding from said base to a top.

12. The method of claim 11 wherein said base is rectangular and said sides include four sides.

13. The method of claim 11 wherein said base is square and said sides include four sides.

14. The method of claim 12 or 13 wherein each of said blocks includes a length ranging from about 5 microns to about 2,000 microns, a width ranging from about 5 microns to about 2,000 microns, and a thickness from said base to said top ranging from about 2 microns to about 500 microns.

15. The method of claim 1 wherein a pump recirculates said slurry over said substrate.

16. The method of claim 1 wherein a mechanical means is used to move said slurry over said substrate.

17. A method of transporting a micromachined block comprising an integrated circuit portion, said method comprising:

placing at least one block in a fluid; and

transporting said block to a selected location.

18. The method of claim 17 wherein a pump transports said block.

19. The method of claim 17 wherein a bubble pump transports said block.

20. The method of claim 17 wherein a jet pump transports said block.

21. The method of claim 17 wherein said block self-aligns into a recessed region of a substrate.

22. The method of claim 17 wherein said block is an etched block.

23. The method of claim 17 wherein a mechanical means is used to move said block and said fluid.

24. A method of forming a hybrid integrated circuit comprising steps of:

providing a first tapered shaped block including a first electronic device portion thereon, and a second electronic device portion;

placing said first tapered shaped block into a first recessed region of a substrate; and

interconnecting said first tapered shaped block with said, second electronic device portion, said interconnecting step being a metallization step.

25. The method of claim 24 wherein said second electronic device portion is located on said substrate.

26. The method of claim 24 wherein said second electronic device portion is located on a second tapered shaped block placed into a second recessed region of said substrate.

27. The method of claim 26 wherein a third electronic device portion located on said substrate is interconnected to said first electronic device portion or to said second electronic device portion.

28. A method of assembling a microstructure on a substrate, said substrate comprising a top surface with at least one recessed region thereon, comprising the steps of:

providing a slurry comprising a plurality of tapered blocks and a fluid, said shaped block including at least a portion of an integrated circuit; and

transferring said slurry over said substrate at a rate where at least one of said shaped blocks is dispensed into a recessed region.