Integrated circuit non-etch technique for forming vias in a semiconductor wafer and a semiconductor wafer having vias formed therein using non-etch technique

• US 5,825,076 A
• Filed: 07/25/1996
• Issued: 10/20/1998
• Est. Priority Date: 07/25/1996
• Status: Expired due to Term

• Current Assignee: Northrop Grumman Corporation
• Original Assignee: Northrop Grumman Corporation
• Inventors: Kotvas, Joseph C., Sriram, Saptharishi
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Hardy, David B.
• Application Number:
  US08/685,884
• Time in Patent Office: 817 Days
• Field of Search: 257/620, 257/622, 257/48, 257/618, 257/623, 257/627, 257/628, 437/226, 437/203
• US Class Current: 257/622
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304

Abstract

A semiconductor wafer and a method of forming vias in a semiconductor wafer having opposite first and second planar surfaces and predetermined thickness includes forming a plurality of first channels of first predetermined depth along a first direction in the first planar surface of the semiconductor wafer and forming a plurality of second channels of second predetermined depth along a second direction in the second planar surface of the semiconductor wafer. The first and second predetermined depths of the channels are selected such that vias are formed through the semiconductor wafer. The channels may be formed by saw cutting or scribing the planar surfaces of the semiconductor wafer. A plurality of circuit devices may be formed on the first planar surface of the semiconductor wafer prior to forming the plurality of first and second channels. A metallic layer is deposited within the vias and on the first and second planar surfaces to provide electrical connection between the circuit devices and the second planar surface of the semiconductor wafer through the vias.

Claims

1. A connection method for a semiconductor wafer having opposite first and second planar surfaces and predetermined wafer thickness, the connection method comprising the steps of:

a) processing the semiconductor wafer to form circuit devices on the first planar surface of the semiconductor wafer;

b) forming a plurality of first channels of first predetermined depth along a first direction in the first planar surface of the semiconductor wafer;

c) forming a plurality of second channels of second predetermined depth along a second direction in the second planar surface of the semiconductor wafer,

the first and second directions being nonparallel and at least one of the first and second predetermined depths of the plurality of first and second channels being greater than half the predetermined wafer thickness such that vias are formed through the semiconductor wafer; and

d) depositing a metallic layer within the vias and on the first and second planar surfaces of the semiconductor wafer to provide electrical connection between the circuit devices and the second planar surface of the semiconductor wafer through the vias.

2. The connection method for a semiconductor wafer of claim 1, wherein said step c) comprises forming the plurality of second channels in the second direction perpendicular to the first direction.

3. The connection method for a semiconductor wafer of claim 1, wherein said steps b) and c) comprise cutting the semiconductor wafer to form the plurality of first and second channels.

4. The connection method for a semiconductor wafer of claim 1, wherein said steps b) and c) comprise scribing the semiconductor wafer to form the plurality of first and second channels.

5. The connection method for a semiconductor wafer of claim 1, wherein the first and second predetermined depths of the plurality of first and second channels are greater than half the predetermined wafer thickness.

6. The connection method for a semiconductor wafer of claim 1, wherein said step a) comprises processing the semiconductor wafer to form the circuit devices on respective corresponding portions of the first planar surface to be located over respective ones of the plurality of second channels.

7. The connection method for a semiconductor wafer of claim 1, wherein said step a) comprises processing the semiconductor wafer to form the circuit devices on respective corresponding portions of the first planar surface to be located over corresponding portions of the second planar surface between pairs of the plurality of second channels.

8. The connection method for a semiconductor wafer of claim 1, wherein the semiconductor wafer comprises silicon carbide.

9. A method of forming vias in a semiconductor wafer having opposite first and second planar surfaces and predetermined wafer thickness, the method comprising the steps of:

a) forming a plurality of first channels of first predetermined depth along a first direction in the first planar surface of the semiconductor wafer; and

b) forming a plurality of second channels of second predetermined depth along a second direction in the second planar surface of the semiconductor wafer,

the first and second directions being nonparallel and at least one of the first and second predetermined depths of the plurality of first and second channels being greater than half the predetermined wafer thickness such that the vias are formed through the semiconductor wafer.

10. The method of forming vias in a semiconductor wafer of claim 9, further comprising the step of:

c) depositing a metallic layer within the vias and on the first and second planar surfaces to provide electrical connection between the first and second planar surfaces of the semiconductor wafer through the vias.

11. The method of forming vias in a semiconductor wafer of claim 9, wherein said step b) comprises forming the plurality of second channels in the second direction perpendicular to the first direction.

12. The method of forming vias in a semiconductor wafer of claim 9, wherein said steps a) and b) comprise cutting the semiconductor wafer to form the first and second channels.

13. The method of forming vias in a semiconductor wafer of claim 9, wherein said steps a) and b) comprise scribing the semiconductor wafer to form the first and second channels.

14. The method of forming vias in a semiconductor wafer of claim 9, wherein the first and second predetermined depths of the plurality of first and second channels are greater than half the predetermined wafer thickness.

15. The method of forming vias of claim 9, wherein the semiconductor wafer comprises silicon carbide.

16. A semiconductor wafer having predetermined wafer thickness and opposing first and second planar surfaces comprising:

a plurality of first channels of first predetermined depth formed in the first planar surface of the semiconductor wafer along a first direction; and

a plurality of second channels of second predetermined depth formed in the second planar surface of the semiconductor wafer in a second direction,

said first and second directions being non-parallel and at least one of said first and second predetermined depths of said plurality of first and second channels being greater than half the predetermined wafer thickness such that vias are formed through the semiconductor wafer.

17. The semiconductor wafer of claim 16, wherein said first direction is perpendicular to said second direction.

18. The semiconductor wafer of claim 16, wherein said plurality of first and second channels are saw-cut channels.

19. The semiconductor wafer of claim 16, wherein said plurality of first and second channels are scribed channels.

20. The semiconductor wafer of claim 16, further comprising a metallic layer deposited within the vias and on the first and second planar surfaces of the semiconductor wafer to provide electrical connection between the first and second planar surfaces.