Programming architecture for a programmable integrated circuit employing antifuses

• US 5,825,200 A
• Filed: 09/17/1997
• Issued: 10/20/1998
• Est. Priority Date: 06/21/1996
• Status: Expired due to Term

• Current Assignee: QuickLogic Corporation
• Original Assignee: QuickLogic Corporation
• Inventors: Kolze, Paige A.
• Primary Examiner(s): Santamauro, Jon
• Assistant Examiner(s): LE, DON P
• Application Number:
  US08/929,655
• Time in Patent Office: 398 Days
• Field of Search: 326/38-41
• US Class Current: 326/38
• CPC Class Codes: H03K 17/223 in field-effect transistor switches
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17764 for reliability
• CPC Class Codes: H03K 19/1778 Structural details for adapting physical parameters
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

The programmable interconnect structure of a field programmable gate array (see FIG. 4B) includes a plurality of wire segments extending in a first direction, the wire segments being collinear with respect to each other. An antifuse is disposed between each pair of adjacent wire segments so that the adjacent wire segments can be coupled together. Programming conductors for supplying a programming voltage onto selected wire segments extend in a second direction perpendicular to the first direction. The programming drivers for driving some of the programming conductors are disposed on one side (for example above) of the wire segments whereas the programming drivers for driving others of the programming conductors are disposed on the opposite side (for example below) of the wire segments. The pattern for programming drivers coupled to programming conductors alternates from one side of the wire segments to the other from column to column across the field programmable gate array.

Claims

1. A programmable integrated circuit, comprising:

a plurality of regions, each of the regions having a substantially identical structure, the structure comprising;

a plurality of programming conductors, each of the programming conductors extending substantially parallel to one another in a first dimension;

a plurality of wire segments, each of the wire segments extending substantially parallel to one another in a second dimension perpendicular to the first dimension;

a plurality of programming transistors, each respective programming transistor having one electrode coupled to a corresponding respective one of the programming conductors and having another electrode coupled to a corresponding respective one of the wire segments;

a plurality of antifuses, each respective antifuse being programmable to couple a respective wire segment in the structure to a corresponding respective wire segment in an adjacent one of the substantially identical structures, a wire segment and its corresponding wire segment in the adjacent substantially identical structure being substantially collinear with respect to one another;

a plurality of control conductors, each control conductor extending in the second dimension, each respective one of the control conductors being coupled to gate electrodes of the programming transistors coupled to collinear wire segments;

a first plurality of programming drivers coupled to selected ones of the programming conductors of one of the substantially identical structures B, all of the first plurality of programming drivers being disposed on one side of the control conductors of structure B; and

a second plurality of programming drivers coupled to selected ones of the programming conductors of another of the substantially identical structures C, structure B being adjacent programming drivers being disposed on the opposite side of the control conductors of structure B from the first programming drivers, a programming conductor X in structure B being coupled to one of the first plurality of programming drivers but not being coupled to one of the second plurality of programming drivers, a programming conductor Y in the structure C corresponding with the programming conductor X in structure B being coupled to one of the second plurality of programming drivers but not being coupled to one of the first plurality of programming drivers.

2. The programmable integrated circuit of claim 1, wherein the programming conductors of structures B and C extend in a vertical dimension, and wherein the programming conductor X is the right-most programming conductor of structure B, and wherein the programming conductor Y is the right-most programming conductor of structure C.

3. The programmable integrated circuit of claim 1, wherein the first plurality of programming drivers is disposed substantially in a first row, the first row extending parallel to and adjacent a first side of the programmable integrated circuit, and wherein the second plurality of programming drivers is disposed substantially in a second row, the second row extending parallel to and adjacent a second side of the programmable integrated circuit.

4. The programmable integrated circuit of claim 1, wherein the programmable integrated circuit has a first programming voltage input terminal, a second programming voltage input terminal, and a ground terminal, the programmable integrated circuit further comprising:

a programming current multiplexer having a first input lead coupled to the first programming voltage input terminal, a second input lead coupled to the second programming voltage input terminal, and an output lead coupled to each of the first plurality of programming drivers.