Integrated circuit with field programmable and application specific logic areas

• US 5,825,202 A
• Filed: 09/26/1996
• Issued: 10/20/1998
• Est. Priority Date: 09/26/1996
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Trimberger, Stephen M., Yee, Wilson K., Tavana, Danesh
• Primary Examiner(s): Tokar, Michael J.
• Assistant Examiner(s): ROSEEN, RICHARD R
• Application Number:
  US08/721,392
• Time in Patent Office: 754 Days
• Field of Search: 326/39, 326/41
• US Class Current: 326/39
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

A heterogeneous integrated circuit device comprising a field programmable gate array (FPGA) programmably connected to a mask-defined application specific logic area (ASLA) on an integrated circuit thus providing a flexible low cost alternative to a homogeneous device of one type or the other. By integrating both on a single monolithic IC, the user benefits from both low cost and flexibility. Routing of signals between gate arrays and between the gate arrays and input/output (I/O) circuits is also implemented as a combination of mask-defined and programmably-configured interconnections.

Claims

1. A monolithic integrated circuit comprising:

an array of field programmable gates selectively interconnected by programmable switch matrices, said gates and said switch matrices being selectively programmable after manufacture in accordance with desired gate functions and connection relationships;

an array of mask-defined gates having permanent customized functions and connection relationships;

a plurality of input/output pads providing externally accessible signal connections to said arrays of programmable gates and mask-defined gates; and

a plurality of first interconnections between said arrays of programmable gates and mask-defined gates, said first interconnect ions comprising arrays of programmable and mask-defined interconnections.

2. The integrated circuit recited in claim 1 wherein said plurality of first interconnections comprises a first matrix of field programmable interconnections and a second matrix of mask-defined permanent interconnections, said first matrix and said second matrix each having a plurality of selectable intersecting rows and columns of electrically conductive paths, the respective rows of said first matrix being connected to corresponding rows of said second matrix.

3. The integrated circuit recited in claim 1 further comprising a plurality of second interconnections between said array of programmable gates and a portion of said plurality of input/output pads.

4. The integrated circuit recited in claim 3 wherein said plurality of second interconnections comprises a first matrix of field programmable interconnections and a second matrix of mask-defined permanent interconnections, said first matrix and said second matrix each having a plurality of selectably intersecting rows and columns of electrically conductive paths, the respective rows of said first matrix being connected to corresponding rows of said second matrix.

5. The integrated circuit recited in claim 1 further comprising a plurality of third interconnections between said array of mask-defined gates and a portion of said plurality of input/output pads.

6. The integrated circuit recited in claim 5 wherein said plurality of third interconnections comprises a first matrix of field programmable interconnections and a second matrix of mask-defined permanent interconnections, said first matrix and said second matrix each having a plurality of selectably intersecting rows and columns of electrically conductive paths, the respective rows of said first matrix being connected to corresponding rows of said second matrix.

7. The integrated circuit recited in claim 1 further comprising a plurality of clock pads providing externally accessible clock connections to said arrays of programmable gates and mask-defined gates.

8. The integrated circuit recited in claim 7 wherein at least one of said clock pads is programmably connectable to both of said arrays.

9. The integrated circuit recited in claim 1 wherein said plurality of first interconnections between said arrays of programmable gates and said mask-defined gates comprises a plurality of long lines extending past more than one of said field programmable gates and connected to at least one of said switch matrices.

10. The integrated circuit of claim 1 wherein said plurality of first interconnections occupy integrated-circuit resources substantially separate from integrated-circuit resources occupied by said array of field programmable gates.

11. The integrated circuit of claim 3 wherein said plurality of second interconnections occupy integrated-circuit resources substantially separate from integrated-circuit resources occupied by said array of field programmable gates.

12. The integrated circuit of claim 5 wherein said plurality of third interconnections occupy integrated-circuit resources substantially separate from integrated-circuit resources occupied by said array of field programmable gates.

13. An integrated circuit chip comprising:

a field-configured array of logic blocks having logic functions and being interconnected in accordance with user provided data which may be modified to alter the field-configured array of logic blocks to have different respective logic functions and interconnections;

a mask-defined array of logic blocks having respective logic functions and being interconnected in accordance with selected metal masks which, once selected, cannot be modified; and

an interconnect structure for connecting said field-configured array to said mask-defined array, said interconnect structure comprising arrays of field-configured and mask-defined interconnections.

14. The integrated circuit chip recited in claim 13 wherein each of said arrays occupies a respective distinct portion of said chip.

15. The integrated circuit chip recited in claim 13 wherein said interconnect structure comprises signal routing having a plurality of selectable interconnections, some of said interconnections being mask-defined and some of said interconnections being field selectable by programming.

16. The integrated circuit chip recited in claim 15 wherein said mask-defined interconnections and said field selectable interconnections comprise matrices configured as columns and rows.

17. An integrated circuit configured as a monolithic chip and comprising:

a plurality of logic blocks the logic functions of which may be configured after packaging of said chip, said blocks being interconnected by configurable interconnects in the form of paths which may also be configured after packaging of said chip; and

an array of mask-defined logic gates the logic functions of which are selected before packaging of said chip, said gates being interconnected by paths selected before packaging of said chip, said paths comprising an interconnect-element array;

said logic blocks and said gates being interconnected by paths at least some of which may be configured after packaging of said chip.

18. A method of fabricating an integrated circuit with field programmable and application specific logic areas, the method comprising the following steps:

a) providing an array of mask defined logic gates;

b) providing an array of field programmable logic gates;

c) programming unalterable logic functions of said mask defined logic gates;

d) providing a structure for programming alterable logic functions of said field programmable logic gates; and

e) providing and programming arrays of field-configured and mask-defined interconnections between said mask defined logic gates and said field programmable logic gates.

19. A monolithic integrated circuit comprising:

an array of field programmable gates selectively interconnected by programmable switch matrices, said gates and said switch matrices being selectively programmable after manufacture in accordance with desired gate functions and connection relationships;

an array of mask-defined gates having permanent customized functions and connection relationships;

a plurality of input/output pads providing externally accessible signal connections to said arrays of programmable gates and mask-defined gates; and

a plurality of first interconnections between said arrays of programmable gates and mask-defined gates, said first interconnections comprising programmable interconnections dedicated to the function of interconnecting the field programmable gates to the mask-defined gates.

20. An integrated circuit chip comprising:

a field-configured array of logic blocks having logic functions and being interconnected in accordance with user provided data which may be modified to alter the field-configured array of logic blocks to have different respective logic functions and interconnections;

a mask-defined array of logic blocks having respective logic functions and being interconnected in accordance with selected metal masks which, once selected, cannot be modified; and

an interconnect structure for connecting said field-configured array to said mask-defined array, said interconnect structure comprising programmable interconnections dedicated to the function of interconnecting the field programmable gates to the mask-defined gates.