Amplifier-less low power switched-capacitor techniques
First Claim
1. A switched-capacitor gain-boost network comprising:
- a plurality of sampling charge storing devices having substantially similar charge storing characteristics, said plurality of sampling charge storing devices being connectable to an output node;
an integrating charge storing device connected to said output node and connectable to said plurality of sampling charge storing devices in parallel; and
switch means actuable during a sampling period to connect each of said sampling charge storing devices in parallel and between an analog signal input node and a first node and actuable during an integrating period to connect each of said sampling charge storing devices in series and between a low potential node and said output node wherein during said sampling period said switch means is actuated to inhibit injection charge errors from being applied to said integrating charge storage device by said sampling charge storage devices and wherein during said integrating period said switch means is actuated to inhibit voltage add-up from occurring across said sampling charge storage devices.
1 Assignment
0 Petitions
Accused Products
Abstract
A switched-capacitor gain-boost network includes a bank of N-substantially identical sampling capacitors connectable to an output node. An integrating capacitor has one node connected to a low potential node and a second node connected to the output node. The integrating capacitor is connected to the bank of sampling capacitors in parallel when the bank of sampling capacitors is connected to the output node. Sampling period switches are actuable during a sampling period to connect the sampling capacitors of the bank in parallel and to connect the bank between an analog signal input node and a low potential node to charge the sampling capacitors. Integrating period switches are actuable during an integrating period to connect the sampling capacitors of the bank in series and to connect the bank between a low potential node and the output node to dump the charge stored by the sampling capacitors onto the integrating capacitor. A method of providing dc gain to an analog input signal is also provided.
-
Citations
14 Claims
-
1. A switched-capacitor gain-boost network comprising:
-
a plurality of sampling charge storing devices having substantially similar charge storing characteristics, said plurality of sampling charge storing devices being connectable to an output node; an integrating charge storing device connected to said output node and connectable to said plurality of sampling charge storing devices in parallel; and switch means actuable during a sampling period to connect each of said sampling charge storing devices in parallel and between an analog signal input node and a first node and actuable during an integrating period to connect each of said sampling charge storing devices in series and between a low potential node and said output node wherein during said sampling period said switch means is actuated to inhibit injection charge errors from being applied to said integrating charge storage device by said sampling charge storage devices and wherein during said integrating period said switch means is actuated to inhibit voltage add-up from occurring across said sampling charge storage devices. - View Dependent Claims (2, 3, 4, 5, 6)
-
-
7. A switched-capacitor lowpass filter comprising:
-
a bank of substantially identical sampling capacitors Cr1 to CrN connectable to an output node; an integrating capacitor connected between said output node and a low potential node, said integrating capacitor being connectable in parallel with said bank of sampling capacitors; a plurality of first switches actuable during a sampling period to connect the sampling capacitors of said bank in parallel and to connect said bank between an analog signal input node and a first node to charge each of said sampling capacitors; and a plurality of second switches actuable during an integrating period to connect the sampling capacitors of said bank in series and to connect said bank between a low potential node and said output node wherein after said sampling period, the first switch connecting said sampling capacitor CrN to said analog signal input node is opened prior to opening the remaining first switches and wherein during said integrating period, the second switch connecting said sampling capacitor CrN to said output node is closed prior to closing the remaining second switches. - View Dependent Claims (8, 9, 10)
-
-
11. A method of providing dc gain to an analog input signal comprising the steps of:
-
(i) during a sampling period, connecting a plurality of substantially identical sampling capacitors in parallel and charging each of said sampling capacitors; and (ii) during an integrating period isolating said sampling capacitors from said analog input signal;
connecting said sampling capacitors in series; and
connecting the series-connected sampling capacitors to an output node and in parallel with an integrating capacitor wherein during said sampling period said sampling capacitors are isolated from said analog input signal in a manner to inhibit injection charge errors from being applied to said integrating capacitor by said sampling capacitors and wherein during said integrating period said sampling capacitors are connected in series and to said output node in a manner to inhibit voltage add-up from occurring across said sampling capacitors. - View Dependent Claims (12)
-
-
13. An amplifierless switched-capacitor network comprising:
-
a plurality of generally identical sampling capacitors Cr1 to CrN, one of said sampling capacitors CrN being connectable to an output node by way of a first switch and to a low potential node by way of a second switch; an integrating capacitor connected to said output node and to ground; a plurality of third switches actuable during a sampling period to connect said sampling capacitors in parallel; a plurality of fourth switches actuable during an integrating period to connect said sampling capacitors in series; and timing circuitry to apply clock signals to said first, second, third and fourth switches to actuate said switches between open and closed conditions wherein during said sampling period, said timing circuitry actuates said third switches to connect said sampling capacitors Cr1 to CrN-1 to an analog signal input node and to a dc node and actuates said second switch to connect said sampling capacitor CrN to said analog signal input node and to said low potential node;
following said sampling period, said timing circuitry actuates said second switches to isolate sampling capacitor CrN from said analog signal input node and said low potential node prior to actuating said second switches to isolate said sampling capacitors Cr1 to CrN-1 from said analog signal input node and dc node; and
during said integrating period, said timing circuitry actuates said first switch to connect said sampling capacitor CrN to said output node prior to actuating said fourth switches to connect said sampling capacitors in series. - View Dependent Claims (14)
-
Specification