Phase-locked-loop with noise shaper

• US 5,825,253 A
• Filed: 07/15/1997
• Issued: 10/20/1998
• Est. Priority Date: 07/15/1997
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Younis, Saed G., Mathe, Lennart Karl-Axel
• Primary Examiner(s): MIS, DAVID C
• Application Number:
  US08/893,267
• Time in Patent Office: 462 Days
• Field of Search: 331/1 A, 331/16, 331/18, 331/25, 327/105, 327/115, 327/156-159, 375/376, 455/260
• US Class Current: 331/18
• CPC Class Codes: H03L 7/183 a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number H03L7/1806 takes precedence

Abstract

A phase lock loop wherein the reference clock is divided by a variable divider which is capable of dividing the reference clock by a divider ratio of 2, 3, 4, . . . or M depending on the value of a control signal. The control signal is generated from a divider controller in response to a controller input. The noise shaping characteristics of the divider controller results in dithering of the variable divider ratios such that the average frequency of the divided reference clock is at the desired comparison frequency but the quantization noise from the fractional divide is pushed from low frequency to high frequency where it is more easily filtered. The noise shaper can be implemented with many bits of resolution to allow for a wide frequency control range and high frequency accuracy. A dither circuit to prevent limit cycling at the output of the noise shaper.

Claims

1. A circuit for providing an event clock having improved phase noise characteristics comprising:

a divider controller having an input for receiving an input value and an output, said divider controller producing a control signal at said output in response to said input value; and

a variable divider having an divider input for receiving a reference clock, a control input connected to said output of said divider controller, and an output, said variable divider producing said event clock at said output having cycle widths in response to said control signal.

2. The circuit of claim 1 wherein said divider controller comprises a noise shaper, said noise shaper having and input for receiving said input value and an output;

and

wherein said control signal is dependent on said output of said noise shaper.

3. The circuit of claim 2 wherein said divider controller further comprises a dither circuit, said dither circuit having and output to said input of said noise shaper.

4. The circuit of claim 3 wherein said dither circuit comprises a PN generator having an output, wherein said output of said PN generator is said output of said dither circuit.

5. The circuit of claim 1 wherein said variable divider divides said reference clock by M where M is an integer which is dependent on said control signal.

6. A phase lock loop circuit for providing a clock signal having improved phase noise characteristics comprising:

a divider controller having an input for receiving an input value and an output, said divider controller producing a control signal at said output in response to said input value; and

a variable divider having an divider input for receiving a reference clock, a control input connected to said output of said divider controller, and an output, said variable divider producing said event clock at said output having cycle widths in response to said control signal;

an oscillator having an input and an output, said oscillator producing a clock signal at said output, said clock signal having a frequency which is responsive to said input;

a divider having an input connected to said output of said oscillator and an output, said divider dividing said clock signal

a phase detector having two inputs and an output, one input connected to said output of said variable divider and another input connected to said output of said divider; and

a loop filter having an input connected to said output of said phase detector and an output connected to said input of said oscillator.

7. The circuit of claim 6 wherein said divider controller comprises a noise shaper, said noise shaper having and input for receiving said input value and an output;

and

wherein said control signal is dependent on said output of said noise shaper.

8. The circuit of claim 6 wherein said divider is a fixed N divider, where N is an integer.

9. An apparatus for providing an event clock having improved phase noise characteristics comprising:

noise shaping means for receiving a controller input and providing a control signal in response to said controller input; and

variable divider means for receiving a reference clock and said control signal, said variable divider means dividing said reference clock by a divide ratio corresponding to a value of said control signal.

10. The apparatus of claim 9 wherein said noise shaping means comprises a second order noise shaper.

11. The apparatus of claim 9 wherein said noise shaping means comprises a fourth order noise shaper.

12. The apparatus of claim 9 wherein said variable divider means divides said reference clock by M where M is an integer which is dependent on said value of said control signal.

13. The apparatus of claim 9 wherein noise shaping means has over 16 bits of resolution.

14. An apparatus for providing a clock signal having improved phase noise characteristics comprising:

noise shaping means for receiving a controller input and providing a control signal in response to said controller input;

variable divider means for receiving a reference clock and said control signal, said variable divider means dividing said reference clock by a divide ratio corresponding to a value of said control signal;

oscillator means for receiving a control voltage and producing a clock signal having a frequency which is responsive to said control voltage;

divider means for receiving said clock signal and dividing said clock signal to obtain a divided clock signal;

phase detector means for receiving said event clock and said divided clock signal, said phase detector means producing an error signal in response to a phase of said clock signal and a phase of said divided clock signal;

loop filter means for receiving said error signal, said loop filter means filtering said error signal to obtain said control voltage.

15. The apparatus of claim 14 wherein said noise shaping means comprises a second order noise shaper.

16. The apparatus of claim 14 wherein said noise shaping means comprises a fourth order noise shaper.

17. The apparatus of claim 14 wherein said variable divider means divides said reference clock by M where M is an integer which is dependent on said value of said control signal.

18. The apparatus of claim 14 wherein noise shaping means has over 16 bits of resolution.

19. A method for providing an event clock having improved phase noise characteristics comprising the steps of:

receiving a controller input and a reference clock;

producing a control signal which is noise shaped in response to said controller input; and

dividing said reference clock by a divider ratio corresponding to said control signal to obtain said event clock.

20. A method for providing a clock signal having improved phase noise characteristics comprising the steps of:

receiving a controller input and a reference clock;

producing a control signal which is noise shaped in response to said controller input;

dividing said reference clock by a divider ratio corresponding to said control signal to obtain said event clock;

producing a clock signal in response to a control voltage;

dividing said clock signal by a second divider ratio to obtain a divided clock signal;

phase comparing said event clock and said divided clock signal and to produce an error signal; and

filtering said error signal to obtain said control voltage.