Image processing system including a variable size memory bus

• US 5,825,372 A
• Filed: 06/29/1994
• Issued: 10/20/1998
• Est. Priority Date: 06/30/1993
• Status: Expired due to Term

• Current Assignee: SGS Thomson Microelectronics SA (STMicroelectronics NV)
• Original Assignee: SGS Thomson Microelectronics SA (STMicroelectronics NV)
• Inventors: Artieri, Alain
• Primary Examiner(s): Swann, Tod R.
• Assistant Examiner(s): Chow, Christopher S.
• Application Number:
  US08/267,195
• Time in Patent Office: 1,574 Days
• Field of Search: 395/166, 395/375, 395/307, 395/118, 395/162, 395/164, 395/165, 395/507, 395/515, 395/521, 395/523, 395/509, 395/512
• US Class Current: 345/566
• CPC Class Codes: G06F 12/04 Addressing variable-length words or parts of words
• CPC Class Codes: G06F 13/4018 with data-width conversion
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/427 Display on the fly, e.g. simultaneous writing to and reading from decoding memory
• CPC Class Codes: H04N 19/433 characterised by techniques for memory access
• CPC Class Codes: H04N 19/51 Motion estimation or motion compensation
• CPC Class Codes: H04N 19/61 in combination with predictive coding

Abstract

A system incorporates a processor that includes a data bus having a fixed N-bits size connected to an n-bits word memory through a bus having an n-bits size, where N is a multiple of n, and n is a variable value. The system includes means for, at each execution by the processor of a write instruction of one word of N bits in the memory, successively writing each sub-word of n bits constituting this word of N bits at distinct addresses, and means for, at each execution of a read instruction of a word of N bits in the memory, successively reading in this memory at distinct addresses sub-words of n bits, and juxtaposing these sub-words on the fixed size bus.

Claims

1. An image processing system including an image processor adapted to process images according to intra, predicted and bidirectional modes, in cooperation with a memory capable of storing at least three decoded images and accessible through an N-bit data bus, and adapted to process images only according to intra and predicted modes in cooperation with a half-size memory through an N/2-bit bus, said image processing system comprising:

means for, at each execution by the processor of a write instruction of one N-bit word to the half-size memory, successively writing each N/2-bit sub-word of the N-bit word;

means for, at each execution of a read instruction of an N-bit word from the half-size memory, successively reading in said half-size memory two N/2-bit sub-words, and juxtaposing these subwords on the N-bit bus;

an addressing circuit for providing the half-size memory with two distinct addresses for each address provided by the processor;

an address folding circuit for providing an address within the address boundaries of the half-size memory when an address provided by the addressing means is out of the boundaries; and

means for stopping the processor if an address provided to the half-size memory in write mode corresponds to data which has not yet been read.

2. The system of claim 1, including means for locking each read and write instruction in the processor, so that a same read and write instruction is executed twice.

3. The system of claim 2, wherein said locking means include means for inhibiting the incrementation of an instruction pointer of the processor.

4. The system of claim 2, wherein said locking means include means for inhibiting the provision of a clock signal to the processor.

5. The system of claim 2, wherein said addressing circuit includes means for multiplying each address provided by the processor by two and for incrementing the resulting address after the first execution of the same read and write instructions.

6. The system of claim 2, further comprising:

devices that are connected in order to recieve N-bit data from the N-bit bus through activation of respective enabling signals, each signal being normally activated at each execution of a read instruction, and

means for authorizing the activation of said enabling signals only during the execution of the second of two same read instructions.

7. The system of claim 2, further comprising:

devices that are connected to write N-bit data on the N-bit bus through activation of respective enabling signals, each signal being normally activated each time a write instruction is executed, and

means for authorizing the activation of said enabling signals only during the execution of the first of two same write instructions.

8. A processing system for decoding images encoded in accordance with intra and predicted modes standard, said system comprising:

a memory having an image field;

a processor for decoding said images and for storing and retrieving data of decoded images in said memory, said processor providing first addresses for storing and retrieving said data which include addresses which are larger than said image field; and

address adjusting means for converting said first addresses to second addresses which are within said image field.

9. The processing system of claim 8, wherein said address adjusting means determines said second addresses such that said data are stored in a portion of said memory having data which have been displayed.

10. The processing system of claim 9, further comprising processor control means for controlling operation of said processor such that decoded data to be stored in said memory are not stored over data in said memory which have not been displayed.

11. The processing system of claim 8 wherein said address adjusting means includes:

address generating means for generating a plurality of said second addresses corresponding to each first address;

data division means for separating said decoded data into a plurality of subportions corresponding to said plurality of second addresses, and for storing said subportions of data at respective second addresses in said memory when data are to be stored in said memory; and

data combination means for retrieving subportions of data corresponding to said plurality of second addresses from said memory and for combining said retrieved subportions of data to form said decoded data.

12. The processing system of claim 11, wherein said data division means includes a shift register.

13. The processing system of claim 11, wherein said data combination means includes a shift register.

14. The processing system of claim 10, wherein said processor control means includes:

line counting means for determining the number of lines of a first image which have been displayed;

block counting means for determining the number of blocks of an second image which have been decoded; and

comparator means for inhibiting operation of said processor when said number of blocks exceeds a certain number proportional to said number of lines.

15. The processing system of claim 14, wherein images are displayed in a progressive display mode, wherein said image field is the size of one and a half images, and wherein said certain number is

16. The processing system of claim 14, wherein images are displayed in a interleaved display mode, wherein said image field is the size of one and a half images, and wherein said certain number is

17. A method for decoding and displaying images encoded in accordance with intra and predicted modes standard, said method comprising the steps of:

decoding said images to produce image data;

generating first addresses for storing said image data;

adjusting said first addresses to create a second addresses for storing said image data; and

storing said image data in a memory at locations corresponding to said second addresses.

18. The method of claim 17, further comprising the steps of:

generating said first addresses for retrieving said image data;

adjusting said first addresses to create said second addresses for retrieving said image data;

retrieving said data from said second addressees in said second memory; and

displaying said image data.

19. The method of claim 18, wherein said first addresses are adjusted such that said image data are stored in a portion of said memory having data which has been displayed.

20. The method of claim 19, further comprising the step of inhibiting said decoding step such that decoded data to be stored in said memory are not stored over data in said memory which have not been displayed.

21. The method of claim 17, wherein said address adjusting steps include the step of generating a plurality of said second addresses corresponding to each first addresses;

wherein said storing step includes the steps of;

separating said decoded data into a plurality of subportions corresponding to said plurality of second address, and storing said subportions of data at said respective second addresses in said memory; and

wherein said retrieving step includes the steps of;

retrieving subportions of data corresponding to said plurality of second addresses from said memory, and

combining said retrieved subportions of data to form said image data.

22. The method of claim 20, wherein said inhibiting step includes the steps of:

determining the number of lines of a first image which have been displayed;

determining the number of blocks of a second image which have been decoded; and

inhibiting operation of said decoding step when said number of blocks exceeds a certain number proportional to said number of lines.