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Image processing system including a variable size memory bus

  • US 5,825,372 A
  • Filed: 06/29/1994
  • Issued: 10/20/1998
  • Est. Priority Date: 06/30/1993
  • Status: Expired due to Term
First Claim
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1. An image processing system including an image processor adapted to process images according to intra, predicted and bidirectional modes, in cooperation with a memory capable of storing at least three decoded images and accessible through an N-bit data bus, and adapted to process images only according to intra and predicted modes in cooperation with a half-size memory through an N/2-bit bus, said image processing system comprising:

  • means for, at each execution by the processor of a write instruction of one N-bit word to the half-size memory, successively writing each N/2-bit sub-word of the N-bit word;

    means for, at each execution of a read instruction of an N-bit word from the half-size memory, successively reading in said half-size memory two N/2-bit sub-words, and juxtaposing these subwords on the N-bit bus;

    an addressing circuit for providing the half-size memory with two distinct addresses for each address provided by the processor;

    an address folding circuit for providing an address within the address boundaries of the half-size memory when an address provided by the addressing means is out of the boundaries; and

    means for stopping the processor if an address provided to the half-size memory in write mode corresponds to data which has not yet been read.

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