Power supply ESD protection circuit

• US 5,825,601 A
• Filed: 06/16/1997
• Issued: 10/20/1998
• Est. Priority Date: 06/16/1997
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Spielberger, Kevin, Suh, Dongwook Drew, Statz, Timothy V.
• Primary Examiner(s): Gaffin, Jeffrey A.
• Assistant Examiner(s): SHERRY, MICHAEL JUDE
• Application Number:
  US08/876,925
• Time in Patent Office: 491 Days
• Field of Search: 361/56, 361/91, 361/111
• US Class Current: 361/56
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements

Abstract

An electrostatic discharge (ESD) protection circuit includes first and second supply terminals, a current source, a shunt transistor, an inverter and a voltage level shifting device. The shunt transistor is coupled between the first and second supply terminals and has a control terminal. The inverter includes an input coupled to the current source, an output coupled to the control terminal of the shunt transistor and pull-up and pull-down transistors coupled between the first and second supply terminals. The pull-up and pull-down transistors have control terminals which are coupled to the input. The voltage level shifting device is coupled between the input and the control terminal of one of the pull-up and pull-down transistors.

Claims

1. An electrostatic discharge (ESD) protection circuit comprising:

first and second supply terminals;

a current source;

a shunt transistor coupled between the first and second supply terminals and having a control terminal;

an inverter comprising an input coupled to the current source, an output coupled to the control terminal of the shunt transistor, and pull-up and pull-down transistors coupled between the first and second supply terminals, the pull-up and pull-down transistors having control terminals which are coupled to the input; and

a voltage level shifting device coupled between the input and the control terminal of one of the pull-up and pull-down transistors.

2. The ESD protection circuit of claim 1 wherein the voltage level shifting device comprises a level shifting transistor coupled as a source-follower between the input and the control terminal of one of the pull-up and pull-down transistors.

3. The ESD protection circuit of claim 1 wherein the voltage level shifting device comprises a plurality of level shifting transistors coupled in cascade with one another as source-followers between the input and the control terminal of one of the pull-up and pull-down transistors.

4. The ESD protection circuit of claim 1 and further comprising a charge holding device which is coupled in series with the current source between the first and second supply terminals.

5. The ESD protection circuit of claim 4 wherein the charge holding device comprises a transistor having a source and drain coupled to one of the first and second supply terminals and a gate coupled to the current source.

6. The ESD protection circuit of claim 4 wherein the capacitor comprises a parallel plate capacitor.

7. The ESD protection circuit of claim 1 wherein the current source comprises a resistor.

8. The ESD protection circuit of claim 1 wherein:

the shunt transistor comprises an N-channel shunt transistor having a gate, a drain coupled to the first supply terminal and a source coupled to the second supply terminal;

the pull-up transistor comprises a P-channel pull-up transistor having a gate coupled to the input, a source coupled to the first supply terminal and a drain coupled to the gate of the N-channel shunt transistor;

the pull-down transistor comprises an N-channel pull-down transistor having a gate, a drain coupled to the gate of the N-channel shunt transistor and a source coupled to the second supply terminal; and

the level shifting device comprises an N-channel level shifting transistor having a gate coupled to the input, a drain coupled to the first supply terminal and a source coupled to the gate of the N-channel pull-down transistor.

9. The ESD protection circuit of claim 1 wherein:

the shunt transistor comprises an P-channel shunt transistor having a gate, a source coupled to the first supply terminal and a drain coupled to the second supply terminal;

the pull-up transistor comprises a P-channel pull-up transistor having a gate, a source coupled to the first supply terminal and a drain coupled to the gate of the P-channel shunt transistor;

the pull-down transistor comprises an N-channel pull-down transistor having a gate coupled to the input, a drain coupled to the gate of the P-channel shunt transistor and a source coupled to the second supply terminal; and

the level shifting device comprises an P-channel level shifting transistor having a gate coupled to the input, a drain coupled to the second supply terminal and a source coupled to the gate of the P-channel pull-up transistor.

10. An integrated circuit die comprising:

a plurality of semiconductor cells;

first and second power supply conductors which have different relative polarities and are electrically coupled to the plurality of semiconductor cells; and

an electrostatic discharge (ESD) protection circuit comprising;

a current source coupled to one of the first and second power supply conductors;

a shunt transistor coupled between the first and second power supply conductors and having a control terminal;

an inverter comprising a pull-up transistor and a pull-down transistor which are coupled between the control terminal of the shunt transistor and the first and second power supply conductors, respectively, and which have control terminals which are coupled to the current source; and

a voltage level shifting device coupled between the current source and the control terminal of one of the pull-up and pull-down transistors.

11. The integrated circuit die of claim 10 wherein the ESD protection circuit further comprises a capacitor coupled in series with the current source between the first and second power supply conductors.

12. The integrated circuit die of claim 11 wherein the capacitor comprises a transistor.

13. The integrated circuit die of claim 10 wherein the capacitor comprises a parallel plate capacitor formed on the integrated circuit die.

14. The integrated circuit die of claim 10 wherein the voltage level shifting device comprises a level shifting transistor coupled as a source-follower between the current source and the control terminal of one of the pull-up and pull-down transistors.

15. An electrostatic discharge (ESD) protection circuit comprising:

first and second supply terminals;

a current source coupled to one of the first and second supply terminals;

a shunt transistor having first and second terminals coupled to the first and second supply terminals, respectively, and having a control terminal; and

an inverter formed by a pull-up transistor and a pull-down transistor coupled between the first and second supply terminals and having an input coupled to the current source and an output coupled to the control terminal of the shunt transistor; and

means for creating a voltage difference between the inverter input and a control terminal of one of the pull-up and pull-down transistors.