Method and apparatus for automatic post-layout optimization of an integrated circuit

• US 5,825,661 A
• Filed: 05/01/1996
• Issued: 10/20/1998
• Est. Priority Date: 05/01/1996
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Drumm, Anthony DeGroff
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): Siek, Vuthe
• Application Number:
  US08/641,390
• Time in Patent Office: 902 Days
• Field of Search: 364/488-491, 364/578, 395/500
• US Class Current: 716/104
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

Automatic generation of post-layout optimization circuitry allows a computer system running an integrated circuit design tool to automatically compensate for timing errors by synthesizing circuit elements to bring the timing within specified timing constraints. A new circuit element is assigned a location without determining an allowable physical location on the integrated circuit, and all timing calculations are based on the assigned location. Then, once the timing constraints have been met by one or more new circuit elements, an incremental layout is performed to find physical locations for the new circuit elements, using the assigned locations as initial targets. By using assigned locations during timing calculations and later determining valid physical locations, many different circuit configurations may be evaluated in a short period of time, with only the best ones going through the more time-consuming step of layout and routing.

Claims

1. A computer-implemented method for synthesizing post-layout optimization circuitry for an integrated circuit design after the layout of functional circuitry on the integrated circuit is complete, the integrated circuit design including a set of timing constraints that must be met for the integrated circuit to operate correctly, the method including the steps of:

(A) automatically generating a new circuit element that changes the timing of at least one of a plurality of nets within the integrated circuit, the new circuit element being an addition to the functional circuitry;

(B) inserting the new circuit element into the integrated circuit design in an assigned location that is anticipated to improve the timing of the integrated circuit design without determining an allowable physical location for the new circuit element;

(C) recalculating the timing for at least one of the plurality of nets within the integrated circuit design based on the topology of the net as determined by the insertion of the new circuit element at the assigned location;

(D) determining whether the recalculated timing violates the timing constraints;

(E) accepting the new circuit element if the recalculated timing improves the timing performance of the integrated circuit design in light of the timing constraints, and discarding the new circuit element if the recalculated timing does not improve the timing performance of the integrated circuit design in light of the timing constraints;

(F) repeating steps A-E until one of the following occurs;

the recalculated timing is within the timing constraints;

the recalculated timing is the closest to the timing constraints as possible while still violating the timing constraints after a predetermined number of repetitions of steps A-E;

(G) determining an allowable location for each accepted new circuit element using the corresponding assigned location as an initial target.

2. The method of claim 1 wherein the layout of the functional circuitry remains substantially unchanged during steps (A) through (F).

3. A method for designing an integrated circuit in a manner that automatically generates post-layout optimization circuitry, when necessary, after the layout of functional circuitry on the integrated circuit is complete, to compensate for at least one timing problem in the integrated circuit, the method comprising the steps of:

(A) synthesizing a logic design for an integrated circuit using an integrated circuit design tool executing on a computer system, the integrated circuit design tool having a plurality of software modules;

(B) providing a set of timing constraints that must be met for the integrated circuit to operate correctly;

(C) generating a physical design for the integrated circuit, the step of generating the physical design including the steps of;

(1) laying out at least one circuit element to implement the logic design;

(2) estimating the timing for at least one signal coupled to the at least one circuit element based on estimated path lengths as determined by the layout;

(3) determining whether the estimated timing violates the timing constraints;

(4) routing a plurality of nets to interconnect the at least one circuit element;

(5) calculating the timing for at least one of the nets based on the physical characteristics of the net as determined by the routing;

(6) determining whether the calculated timing violates the timing constraints;

(7) if the calculated timing violates the timing constraints, synthesizing the post-layout optimization circuitry by performing the steps of;

(7A) automatically generating a new circuit element that is an addition to the at least one circuit element that implements the logic design;

(7B) inserting the new circuit element into the integrated circuit in an assigned location that is anticipated to improve the calculated timing without determining an allowable physical location on the integrated circuit for the new circuit element;

(7C) recalculating the timing for at least one of the nets based on the topology of the net as determined by the insertion of the new circuit element at the assigned location;

(7D) determining whether the recalculated timing violates the timing constraints;

(7E) accepting the new circuit element if the recalculated timing is closer to the timing constraints than the calculated timing, and discarding the new circuit element if the recalculated timing is not closer to the timing constraints than the calculated timing;

(7F) repeating steps 7A-7E until one of the following occurs;

the recalculated timing is within the timing constraints;

the recalculated timing is the closest to the timing constraints as possible while still violating the timing constraints after a predetermined number of repetitions of steps 7A-7E;

(7G) determining an allowable location for each accepted new circuit element using the corresponding assigned location as an initial target.

4. The method of claim 3 wherein the step of synthesizing post-layout optimization circuitry causes the execution of at least one of the software modules that is also executed to synthesize the logic design of the integrated circuit.

5. The method of claim 3 wherein the layout of the at least one circuit element that implements the logic design remains substantially unchanged during steps (7A) through (7G).