Multi-value read-only memory cell having an improved signal-to-noise ratio

• US 5,825,686 A
• Filed: 08/11/1997
• Issued: 10/20/1998
• Est. Priority Date: 02/16/1995
• Status: Expired due to Term

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Siemens AG
• Inventors: Bollu, Michael, Thewes, Roland, Schmitt-Landsiedel, Doris, von Basse, Paul-Werner
• Primary Examiner(s): LE, VU ANH
• Application Number:
  US08/875,955
• Time in Patent Office: 435 Days
• Field of Search: 365/185.03, 365/185.01, 365/94, 365/104, 365/105
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 11/5692 read-only digital stores using storage elements with more than two stable states
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: H01L 29/7923 Programmable transistors with more than two possible different levels of programmation

Abstract

The invention concerns a multi-valued read-only storage location which is constructed symmetrically for storing a first or second state (M, M"'"'"') and asymmetrically for storing at least a third state (M'"'"', M"). The advantage thereof is above all that the storage capacity is doubled without notably increasing expenditure and without impairing the signal-to-noise ratio with respect to conventional storage locations. The invention is suitable for electrically programmable and mask-programmable read-only memories, in particular for those used in low voltage technology.

Claims

1. Multi-value read-only memory cell, having symmetrical construction for storing one of a first state and a second state and having asymmetrical construction for storing at least a third state, comprising:

a MOS field-effect transistor having a source/drain region situated in a semiconductor body and having a drain/source region situated in the semiconductor body;

in order to store the first state, a first cell connection connected directly to the source/drain region of the MOS field-effect transistor and a second cell connection connected directly to the drain/source region of the MOS field-effect transistor;

in order to store the second state, the first cell connection connected via a first component to the source/drain region of the MOS field-effect transistor, and the second cell connection connected via a second component to the drain/source region of the MOS field-effect transistor;

in order to store the third state, the first cell connection connected via the first component to the source/drain region of the MOS field-effect transistor, and the second cell connection connected directly to the drain/source region of the MOS field-effect transistor;

in order to store a fourth state, the first cell connection connected directly to the source/drain region of the MOS field-effect transistor, and the second cell connection connected via the second component to the drain/source region of the MOS field-effect transistor;

a third cell connection connected to a gate electrode of the MOS field-effect transistor, the gate electrode being electrically insulated from the semiconductor body by an insulation layer (ISO); and

the first component being a first diode and the second component being a second diode.

2. The multi-value read-only memory cell according to claim 1,

wherein, in order to form the first diode, the first cell connection is connected via a first supplementary region to the source/drain region of the MOS field-effect transistor and, in order to form the second diode, the second cell connection is connected via a second supplementary region to the drain/source region of the MOS field-effect transistor;

wherein, in order to store the first state, first and the second supplementary regions are bridged by metallic contact links of the first and second connections, which contact links have a deep structure and extend at least as far as the source/drain region and drain/source region;

wherein, in order to store the second state, both the first and the second supplementary regions are contacted only by metallic contact links of the first and second connections, which contact links have a planar configuration and extend only at least as far as the first and second supplementary regions;

wherein, in order to store the third state, only the first supplementary region is bridged by a metallic contact link of the first connection, which contact link has a deep structure and extends at least as far as the source/drain region; and

wherein, in order to store the fourth state, only the second supplementary region is bridged by a metallic contact link of the first connection, which contact link has a deep structure and extends at least as far as the drain/source region.

3. A multi-value read-only memory cell, having symmetrical construction for storing a first state and a second state and having asymmetrical construction for storing at least a third state, comprising:

a MOS field-effect transistor having a source/drain region situated in a semiconductor body and having a drain/source region situated in the semiconductor body;

in order to store the first state a first cell connection connected directly to the source/drain region of the MOS field-effect transistor, and a second cell connection connected directly to the drain/source region of the MOS field-effect transistor;

in order to store the second state, the first cell connection connected via a first component to the source/drain region of the MOS field-effect transistor and the second cell connection connected via a second component to the drain/source region of the MOS field-effect transistor;

in order to store the third state, the first cell connection connected via the first component to the source/drain region of the MOS field-effect transistor, and the second cell connection connected directly to the drain/source region of the MOS field-effect transistor;

in order to store a fourth state, the first cell connection connected directly to the source/drain region of the MOS field-effect transistor, and the second cell connection connected via the second component to the drain/source region of the MOS field-effect transistor;

a third cell connection connected to a gate electrode of the MOS field-effect transistor, the gate electrode being electrically insulated from the semiconductor body by an insulation layer; and

the first component being a first resistor and the second component being a second resistor.