Non-volatile semiconductor storage apparatus

• US 5,825,688 A
• Filed: 06/16/1997
• Issued: 10/20/1998
• Est. Priority Date: 07/26/1994
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation), Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Ueki, Hiroshi
• Primary Examiner(s): LE, VU ANH
• Application Number:
  US08/876,709
• Time in Patent Office: 491 Days
• Field of Search: 365/185.11, 365/185.12, 365/185.16, 365/185.05, 327/314, 327/315, 327/316, 327/317, 327/318
• US Class Current: 365/185.11
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A non-volatile semiconductor storage apparatus which incorporates second bit lines connected to the sources of memory cell transistors arranged in a column direction, formed separately from the layer of first bit lines connected to the drains of the memory cell transistors arranged in a column direction. The apparatus is equipped with a system which can erase data byte by byte without enlarging the whole size irrespective of the provision of decoders in the first and second bit lines. A non-volatile semiconductor storage apparatus which erases data byte by byte by selecting a predetermined group of memory cell transistors by the source lines and the word lines connected to the diffusion area in the groups of memory cell transistors.

Claims

1. A non-volatile semiconductor storage apparatus, comprising:

an array of memory cell transistors arranged in row and column directions;

a first layer having first bit lines connected to drains of said memory cell transistors and extending in the column direction in zigzag form between paired columns of memory cell transistors;

a second layer having second bit lines connected to sources of said memory cell transistors and extending in the column direction;

word lines connected to control gates of said memory cell transistors and extending in the row direction; and

a word line decoder selectively for keeping said word lines at a relatively high potential, an intermediate potential and a ground potential.

2. A non-volatile semiconductor storage apparatus according to claim 1, further comprising:

first bit line decoders for selecting a first bit line from a plurality of first bit lines; and

second bit line decoders for selecting a second bit line from a plurality of second bit lines.