Serial input shift register built-in self test circuit for embedded circuits

• US 5,825,785 A
• Filed: 05/24/1996
• Issued: 10/20/1998
• Est. Priority Date: 05/24/1996
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Chickanosky, John D., Ouellette, Michael R., Oakland, Steven F., Barry, Robert L.
• Primary Examiner(s): Nguyen, Hoa T.
• Application Number:
  US08/653,572
• Time in Patent Office: 879 Days
• Field of Search: 371/22.4, 371/22.3, 371/22.5, 371/27, 371/22.6
• US Class Current: 714/732
• CPC Class Codes: G01R 31/31813 Test pattern generators
• CPC Class Codes: G01R 31/3185 Reconfiguring for testing, e.g. LSSD, partitioning
• CPC Class Codes: G06F 2201/83 the solution involving signatures

Abstract

A highly functional built in self test circuit for embedded compiled macros is useful for testing embedded compiled macros having differing parameters. The built in self test circuit receives a scan vector that describes the parameters of the embedded compiled macro that is to be tested. For, example, the number and width of words stored in a read only memory (ROM) are scanned into the built in self test circuit for controlling the test sequences. A state machine within the built in self test circuit cycles through test vector generation, test vector application, data output scanning and compression for signature analysis. Parallel outputs of the embedded compiled devices are serialized so that regardless of the number of outputs, a serial input shift register can be used for signature generation.

Claims

1. In an integrated circuit chip a method of using a built-in self test circuit for testing an embedded macro circuit on said chip having parallel outputs, said method comprising the steps of:

(a) initializing said chip into a test mode of operation;

(b) generating a test vector in said built-in self test circuit,

(c) applying said test vector to inputs of said embedded macro circuit causing said embedded macro circuit to generate a response on the parallel outputs;

(d) loading said response into a scan register;

(e) serially shifting said response from said scan register into a serial input shift register (SISR); and

(f) repeating steps (b) through (e) such that each subsequent response is serially compressed with a previous response in said SISR resulting in a signature of said each response in said SISR.

2. The method according to claim 1 further comprising a step (g) comparing the signature to a predetermined signature known to represent a fully functional embedded macro circuit.

3. The method according to claim 2 wherein said step (d) loading the scan register is performed by latching said response into the scan register by clocking said scan register such that each output of said parallel outputs is latched in parallel.

4. The method according to claim 2 wherein said step (b) generating a test vector includes complementing portions of said test vector prior to applying a target test vector.

5. The method according to claim 2 wherein said test vector of step (b) is generated pseudo randomly.

6. The method according to claim 2 wherein said test vector of step (b) is generated predictably by stepping a counter.

7. The method according to claim 1 further comprising a step (h) burn-in mode, wherein said steps (b) through (g) are repeated a predetermined number of times under varying environmental conditions for stressing the embedded circuit under burn-in mode conditions.

8. An integrated circuit chip having a flexible built-in self test capability for generating a plurality of test vectors for application to a device within said chip for causing said device to produce at least two parallel outputs in response to each of said plurality of test vectors, said device including a scan register for receiving said at least two parallel outputs, said chip comprising:

control logic for initializing said chip into a test mode in response to a mode select signal applied thereto, said control logic further controlling states of the device for test purposes;

a test vector generator coupled to said control logic and to said device for generating said plurality of test vectors for application to inputs of said device, wherein said device generates said at least two parallel outputs in response to each test vector of said plurality of test vectors; and

a serial input shift register (SISR) coupled to said control logic and to said device wherein said control logic instructs said device to latch each said at least two parallel outputs to be verified into said scan register and then serially shift contents of said scan register into said SISR for each test vector, said SISR generating a signature from said shifted contents.

9. The electronic apparatus according to claim 8 wherein said test vector generator comprises a linear feedback shift register for generating said plurality of test vectors pseudo-randomly.

10. The electronic apparatus according to claim 8 wherein said test vector generator comprises a counter for sequentially generating said plurality of test vectors.

11. The electronic apparatus according to claim 10 wherein said device is a memory device and said test vector generator generates addresses for causing data in said memory to appear at said at least two parallel outputs.

12. An integrated circuit having a plurality of circuits thereon, including an embedded circuit having a plurality of inputs and a plurality of outputs not directly accessible by I/O pads of said integrated circuit, said embedded circuit having a scan register for serializing said plurality of outputs, said integrated circuit further comprising a built-in self test circuit for verifying proper operation of said embedded circuit, said built-in self test circuit comprising:

control logic for controlling a plurality of states of said built-in self test circuit and said embedded circuit, said plurality of states including a test vector state, a load state, and a shift state;

a test generator coupled to said control logic for generating a test vector when said control logic is in said test vector state wherein each said test vector is input to said embedded circuit; and

a serial input shift register coupled to said control logic and coupled to said scan register of said embedded circuit for scanning in said serialized outputs from said scan register when said control logic causes said shift state, wherein a number of said parallel outputs is for determining a number of shifts is provided during said load state, and said serial input shift register generating a signature from said serialized outputs.

13. The integrated circuit according to claim 12 wherein said control logic further includes a burn-in state wherein said embedded circuit is repeatedly cycled through said verification.

14. The integrated circuit according to claim 12 wherein said embedded circuit is a compiled memory having parameterized addresses and parallel outputs.

15. The integrated circuit according to claim 14 wherein said test generator comprises a counter wherein said counter is preloaded with a seed number from said control logic such that a number of counts of said counter is equal to the paramaterized number of addresses.

16. An integrated circuit having a plurality of circuits thereon and a plurality of input/output pads, said integrated circuit comprising:

a compiled read only memory embedded within said integrated circuit having address inputs and parallel data outputs wherein said addresses inputs and said parallel data outputs are not directly accessible by said plurality of input/output pads, said compiled read only memory including a scan register for serializing data from said parallel data outputs;

an address generator for generating each address of said compiled read only memory, said address generator comprising;

an address counter for generating row and column addresses, said address counter able to count more addresses than available in said compiled read only memory, said address counter being incremented or decremented from a predetermined start number;

a true/complement circuit coupled for receiving said row and column addresses from said address counter for providing to the compiled read only memory combinations of a true row address, a true column address, a complemented row address and a complemented column address

a complement counter for controlling those true/complement combinations to be applied to said address inputs; and

a multiplexer coupled for selectively receiving addresses from said integrated circuit or true/complement row and column addresses from said true/complement circuit for application to said compiled read only memory;

a shift counter programmed to count a number of parallel outputs available from said compiled read only memory, said shift counter scanning each output of said parallel outputs out of said scan register for each address applied to said compiled read only memory;

a serial input shift register coupled for receiving the contents from said scan register as each output of said parallel outputs is shifted out; and

a state machine coupled for controlling states necessary for testing said compiled read only memory, said state machine receiving programming data defining parameters of said compiled read only memory including a number of addresses locations and a number of parallel data outputs.