DC-balanced and transition-controlled encoding method and apparatus

• US 5,825,824 A
• Filed: 03/27/1996
• Issued: 10/20/1998
• Est. Priority Date: 10/05/1995
• Status: Expired due to Term

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Silicon Image, Inc. (Lattice Semiconductor Corporation)
• Inventors: Lee, Kyeongho, Jeong, Deog-Kyon
• Primary Examiner(s): Pham, Chi H.
• Assistant Examiner(s): Tran, Khai
• Application Number:
  US08/622,810
• Time in Patent Office: 937 Days
• Field of Search: 375/292, 375/290, 341/58, 341/95, 341/59, 341/52, 341/68, 370/472, 370/473, 371/37.05
• US Class Current: 375/292
• CPC Class Codes: H04L 2007/045 Fill bit or bits, idle words
• CPC Class Codes: H04L 25/03866 using scrambling
• CPC Class Codes: H04L 25/085 Arrangements for reducing interference in line transmission systems, e.g. by differential transmission
• CPC Class Codes: H04L 25/4915 using pattern inversion or substitution H04L25/4908 takes precedence
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04N 21/2368 Multiplexing of audio and video streams
• CPC Class Codes: H04N 21/4341 Demultiplexing of audio and video streams
• CPC Class Codes: H04N 7/083 with signal insertion during the vertical and the horizontal blanking interval , e.g. MAC data signals
• CPC Class Codes: H04N 7/52 Systems for transmission of a pulse code modulated video signal with one or more other pulse code modulated signals, e.g. an audio signal or a synchronizing signal assembling of a multiplex stream by combining a video stream with other content or additional data, remultiplexing of multiplex streams, insertion of stuffing bits into the multiplex stream, assembling of a packetised elementary stream at server side H04N21/236; disassembling of a multiplex stream, remultiplexing of multiplex streams, extraction or processing of Service Information, disassembling of packetised elementary stream at client side H04N21/434

Abstract

A method and apparatus for producing a transition-controlled, DC-balanced sequence of characters from an input sequence of data bytes. The bits in each of the data bytes are selectively complemented in accordance with the number of logical `1` signals in each data byte in order to produce selectively complemented data blocks. A cumulative disparity is then determined between the logical values of different type included within ones of the selectively complemented data blocks previously encoded into characters. In addition, a current disparity in a candidate character associated with a current one of the selectively complemented data blocks being encoded is also determined. The candidate character is assigned to the current one of the selectively complemented data blocks if the current disparity is of a polarity opposite to a first polarity of the cumulative disparity. Alternately, the complement of the candidate character is assigned to the current one of the selectively complemented data blocks if the current disparity is of the first polarity. In a high-transition mode of operation, the bits within data blocks including fewer than a minimum number of logical `1` signals are selectively complemented so that each such selectively complemented data block includes in excess of the minimum number of logical transitions. In a low-transition mode of operation, the bits within data blocks having more than a predefined number of logical `1` signals are selectively complemented so that each such selectively complemented data block includes less than the maximum number of logical transitions.

Claims

1. A method for producing a DC-balanced sequence of characters from an input sequence of 8 bit data blocks, said method including the steps of:

selectively complementing bits in said 8 bit data blocks in accordance with a number of logical signals of predefined type in each said 8 bit data block in order to produce selectively complemented data blocks;

determining a cumulative disparity in the number of logical values of different type included within ones of said selectively complemented data blocks previously encoded into ones of said characters;

determining a current disparity in a candidate character associated with a current one of said selectively complemented data blocks being encoded; and

assigning said candidate character to said current one of said selectively complemented data blocks if said current disparity is of a polarity opposite to a first polarity of said cumulative disparity, and assigning the complement of said candidate character to said current one of said selectively complemented data blocks if said current disparity is of said first polarity.

2. The method of claim 1 wherein said step of selectively complementing includes the step of selectively complementing predetermined ones of said bits in said 8 bit data blocks having fewer than a predetermined number of said logical signals of predefined type.

3. The method of claim 1 wherein said step of selectively complementing includes the step of selectively complementing predetermined ones of said bits in said 8 bit data blocks having more than a predetermined number of said logical signals of predefined type.

4. The method of claim 1 further including the step of setting a predetermined bit in said candidate character to a first logical value when a current 8 bit data block associated therewith has fewer than a predetermined number of logical signals of predefined type, and setting said predetermined bit to the complement of said first logical value otherwise.

5. The method of claim 1 further including the step of setting a predetermined bit said candidate character to a first logical value when a current 8 bit data block associated therewith has more than a predetermined number of logical signals of predefined type, and setting said predefined bit to the complement of said first logical value otherwise.

6. The method of claim 1 wherein the logical value of a predetermined bit in each character assigned to one of said selectively complemented data blocks indicates whether a candidate character or complement thereof was assigned to said selectively complemented data block.

7. The method of claim 1 wherein said step of determining a current disparity in a candidate character includes the step of performing a logic analysis upon bits of said candidate character.

8. The method of claim 1 further including the step of assigning specific ones of said 8 bit data blocks having fewer than a predetermined number of logical signals of predefined type to be representative of special characters, said special characters being encoded distinctly from ones of said 8 bit data blocks not corresponding to ones of said special characters.

9. A binary data encoding apparatus for producing a DC balanced sequence of characters from an input sequence of 8 bit data blocks, said binary data encoding apparatus comprising:

means for selectively complementing bits in said 8 bit data blocks in accordance with a number of logical signals of predefined type in each said 8 bit data block in order to produce selectively complemented data blocks;

means for determining a cumulative disparity in the number of logical values of different type included within ones of said selectively complemented data blocks previously encoded into ones of said characters;

means for determining a current disparity in a candidate character associated with a current one of said selectively complemented data blocks being encoded; and

means for assigning said candidate character to said current one of said selectively complemented data blocks if said current disparity is of a polarity opposite to a first polarity of said cumulative disparity, and assigning the complement of said candidate character to said current one of said selectively complemented data blocks if said current disparity is of said first polarity.

10. The binary data encoding apparatus of claim 9 wherein said means for selectively complementing includes means for selectively complementing predetermined ones of said bits in said 8 bit data blocks having fewer than a predetermined number of said logical signals of predefined type.

11. The binary data encoding apparatus of claim 9 wherein said means for selectively complementing includes means for selectively complementing predetermined ones of said bits in said 8 bit data blocks having more than a predetermined number of said logical signals of predefined type.

12. The binary data encoding apparatus of claim 9 further including means for setting a predetermined bit in said candidate character a first logical value when said current 8 bit data block has fewer than a predetermined number of logical signals of predefined type, and means for setting said predetermined bit to the complement of said first logical value otherwise.

13. The binary data encoding apparatus of claim 9 further including means for setting a predetermined bit in said candidate character to a first logical value when said current 8 bit data block has more than a predetermined number of logical signals of predefined type, and means for setting said predetermined bit to the complement of said first logical value otherwise.

14. The binary data encoding apparatus of claim 9 wherein the logical value of a predetermined bit in each character assigned to one of said selectively complemented data blocks indicates whether a candidate character or complement thereof was assigned to said selectively complemented data block.

15. The binary data encoding apparatus of claim 9 wherein said means for determining a current disparity in a candidate character includes means for performing a logic analysis upon bits of said candidate character.

16. The binary data encoding apparatus of claim 9 further including means for assigning specific ones of said 8 bit data blocks having fewer than a predefined number of logical signals of predefined type to be representative of special characters and for encoding said special characters distinctly from ones of said 8 bit data blocks not corresponding to ones of said special characters.

17. A method for high speed transmission of digital data comprising the steps of:

encoding an input sequence of 8 bit data blocks into a sequence of characters by;

(i) selectively complementing bits in an input sequence of 8 bit data blocks in accordance with the number of logical signals of predefined type in each said 8 bit data block in order to produce selectively complemented data blocks, (ii) determining a cumulative disparity in logical values associated with ones of said selectively complemented data blocks previously encoded into ones of said characters, (iv) determining a current disparity in a candidate character associated with a current one of said selectively complemented data blocks being encoded, and (iv) assigning said candidate character to said current one of said selectively complemented data blocks if said current disparity is of a polarity opposite to a first polarity of said cumulative disparity, and assigning the complement of said candidate character to said current one of said selectively complemented data blocks if said current disparity is of said first polarity;

converting each character into a serial data string; and

transmitting each said serial data string over a serial communication link.