System and method for copy-protecting distributed video content

• US 5,825,879 A
• Filed: 09/30/1996
• Issued: 10/20/1998
• Est. Priority Date: 09/30/1996
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Davis, Derek L.
• Primary Examiner(s): Tarcza, Thomas H.
• Assistant Examiner(s): Laufer, Pinchus M.
• Application Number:
  US08/723,830
• Time in Patent Office: 750 Days
• Field of Search: 380/5, 380/10, 380/20, 380/4, 380/49, 380/52, 380/3
• US Class Current: 380/216
• CPC Class Codes: G06F 21/606 by securing the transmission between two devices or processes
• CPC Class Codes: G06F 21/608 Secure printing
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G06F 21/84 output devices, e.g. displays or monitors
• CPC Class Codes: H04N 2005/91364 the video signal being scrambled
• CPC Class Codes: H04N 21/4143 embedded in a Personal Computer [PC]
• CPC Class Codes: H04N 21/4183 providing its own processing capabilities, e.g. external module for video decoding
• CPC Class Codes: H04N 21/4367 Establishing a secure communication between the client and a peripheral device or smart card
• CPC Class Codes: H04N 21/4405 involving video stream decryption
• CPC Class Codes: H04N 5/913 for scrambling ; for copy protection
• CPC Class Codes: H04N 7/1675 Providing digital key or authorisation information for generation or regeneration of the scrambling sequence pseudo-random number generators in general G06F7/58

Abstract

A secure video content processor ("SVCP") which receives encrypted digital video information and converts it into analog information for a monitor while preventing unauthorized access to the intermediate unencrypted digital data. The SVCP uses hardware envelopes to prevent unauthorized access to the decrypted digital stream. When a need arises to transmit digital data outside the hardware envelope, the digital data is encrypted and then decrypted when it re-enters a hardware protected section of circuitry.

Claims

1. A method of processing graphical data in a secure video content processor, said method comprising the steps of:

decrypting received encrypted video content to generate decrypted video content;

processing decrypted video content to generate a digital image frame;

encrypting the digital image frame and transmitting the encrypted digital image frame to a memory device located outside of the secure video content processor;

retrieving the digital image frame from said memory device and decrypting the digital image frame; and

converting the digital image frame into an analog representation of the digital image frame and transmitting the analog representation to a display device.

2. The method of claim 1 further comprising the step of sending a key from a processor encrypting the digital image frame to a second processor decrypting the digital image frame.

3. The method of claim 2, said method comprising the additional step of authenticating that said second processor is authorized to perform the decrypting before sending the key from said processor encrypting the digital image frame to said second processor.

4. The method of claim 1, wherein the step of processing the decrypted video content includes a decompression of a Joint Photographic Expert Group signal.

5. The method of claim 1 wherein said memory device is a frame buffer memory.

6. A system for processing video data, said system comprising:

a memory unit;

a host processor coupled to said memory unit;

a source of encrypted digital video data;

a cryptographic unit coupled to said host processor, said cryptographic unit decodes and processes the encrypted digital video data from the source to generate frame data, said cryptographic unit includes an encryption unit for encrypting the frame data, said cryptographic unit is encased in a semiconductor package;

a frame buffer which stores said encrypted frame data;

a decryption unit which decrypts the encrypted frame data retrieved from said frame buffer; and

a display device designed to generate a viewable image using output from said decryption unit.

7. The system of claim 6 wherein said display device is a television set.

8. The system of claim 6 wherein said decryption unit further includes a digital to analog converter.

9. The system of claim 6 wherein said decryption unit is located in said display device.

10. A circuit to process encrypted video data within a hardware barrier, the circuit comprising:

a decryption circuit to decrypt encrypted video content and output decrypted video content;

a graphics processor to process the decrypted video content to generate processed video data;

a frame data encryptor to encrypt the processed video data to produce encrypted processed data, said frame data encryptor to transfer the encrypted processed data for storage outside of said hardware barrier; and

a second decryption circuit to retrieve from storage and decrypt the encrypted processed data to output digital image frames.

11. The circuit of claim 10 further comprising a digital to analog converter to convert the digital image frames into an analog video signal for use by a display device.

12. The circuit of claim 10 wherein the hardware barrier is an integrated circuit package.

13. The circuit of claim 10 wherein the hardware barrier destroys said circuit to process encrypted video data when said hardware barrier is opened.