Memory data protection circuit

• US 5,826,007 A
• Filed: 01/21/1997
• Issued: 10/20/1998
• Est. Priority Date: 01/22/1996
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Mori, Kimio, Sakaki, Kinya
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Elmore, Stephen C.
• Application Number:
  US08/785,297
• Time in Patent Office: 637 Days
• Field of Search: 395/183.18, 395/183.03, 395/186, 395/800.32, 395/800.37, 395/800.42, 365/201, 365/185.04, 365/244, 371/51.1, 364/184, 364/550, 364/551.01, 364/481, 364/221.7, 364/244.6, 364/246.6, 364/246.8, 364/246.9, 364/247.3, 364/286.4, 364/286.5, 711/102, 711/103, 711/152
• US Class Current: 714/42
• CPC Class Codes: G01R 31/31701 Arrangements for setting the Unit Under Test [UUT] in a test mode
• CPC Class Codes: G01R 31/31719 Security aspects, e.g. preventing unauthorised access during test
• CPC Class Codes: G06F 11/2236 to test CPU or processors
• CPC Class Codes: G06F 12/1433 for a module or a part of a module
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 8/20 Address safety or protection circuits, i.e. arrangements for preventing unauthorized or accidental access

Abstract

A memory data protection circuit is provided on a one-chip microcomputer having a CPU, ROM, volatile memory, and nonvolatile memory which together with an input/output control circuit are connected to each other via a first bus line. A security flag storage circuit receives a security flag consisting of a plurality of bits. In one state the security flag cannot be rewritten once it has been written. A security flag monitor circuit reads the security flag and when receiving the power-on reset signal recognizes the flag contents. A bus line control circuit controls the connections of the first bus line, a second bus line connected to the ROM, and a third bus line connected to a test-only memory in response to the security flag monitor circuit When the security flag indicates test mode before shipment, the bus line control circuit controls connections so a shift to the test mode may be possible; when it indicates normal operation mode after shipment, a shift to the test mode may be impossible; and when it indicates test mode after shipment, a shift to the test mode may be possible with the ROM disconnected from the second bus line.

Claims

1. A memory data protection circuit provided in a one-chip microcomputer having a CPU, a ROM, a volatile memory, and a nonvolatile memory formed on a single chip, said memory data protection circuit comprising:

a first bus line connected to said CPU, said volatile memory, said nonvolatile memory, and an input/output control circuit;

a second bus line connected to a ROM storing a system program;

a third bus line connected to a test-only memory storing a memory test program;

a security flag storage circuit to which a security flag consisting of a plurality of bits is inputted, into which said security flag is written on receipt of a control signal so that the logic level of said flag may change in one direction, and which stores the security flag in a state where the flag cannot be rewritten once the flag has been written;

a power-on reset circuit that outputs a power-on reset signal when the power supply for the one-chip microcomputer has been turned on;

a security flag monitor circuit that reads the security flag stored in said security flag storage circuit when receiving said power-on reset signal and recognizes the contents of the flag; and

a bus line control circuit which controls the connection of said first bus line, said second bus line and said third bus line according to the recognition result of said security flag monitor circuit, and which controls their connection so that a shift to the test mode may be possible, when said security flag indicates the test mode before shipment, controls their connection so that a shift to the test mode may be impossible, when said security flag indicates the normal operation mode after shipment, and controls their connection so that a shift to the test mode may be possible with said ROM being disconnected from said second bus line, when said security flag indicates the test mode after shipment.

2. A memory data protection circuit according to claim 1, wherein said security flag storage circuit rewrites said security flag consisting of a plurality of bits so that the flag may have a specific pattern according to a combination of the logic levels of a chip enable signal input /CE and a write/read control signal input /WR.

3. A memory data protection circuit according to claim 1, wherein said bus line control circuit further changes the address that said CPU is to executed first to a specific address, when said security flag indicates the test mode after shipment, and said CPU erases the data stored in said nonvolatile memory by executing the contents of the specific address.

4. A memory data protection circuit according to claim 1, wherein said security flag monitor circuit further outputs a signal for erasing the data in said nonvolatile memory, when said security flag indicates the test mode after shipment.

5. A memory data protection circuit provided in a one-chip microcomputer having a CPU, a ROM, a volatile memory, and a nonvolatile memory formed on a single chip, said memory data protection circuit comprising:

a first bus line connected to said CPU, said volatile memory, said nonvolatile memory, and an input/output control circuit;

a second bus line connected to a ROM storing a system program;

a third bus line connected to a test-only memory storing a memory test program;

a security flag storage circuit to which a security flag consisting of a plurality of bits is inputted, into which said security flag is written on receipt of a control signal so that the logic level of said security flag may change in one direction, and which stores the security flag in a state where the flag cannot be rewritten once the flag has been written;

a power-on reset circuit that outputs a power-on reset signal when the power supply for the one-chip microcomputer has been turned on;

a security flag monitor circuit that reads the security flag stored in said security flag storage circuit when receiving said power-on reset signal and recognizes the contents of the flag; and

a bus line control circuit which controls the connection of said first bus line with said CPU according to the recognition result of said security flag monitor circuit and which, when said security flag indicates the test mode before shipment, disconnects said CPU completely from said first bus line and controls said input/output control circuit section so that access to all of the memories may be controlled directly from the input/output terminal to enable a shift to the test mode and which controls the connection so that a shift to the test mode may be impossible, when said security flag indicates the normal operation mode after shipment, and which controls the connection so that a shift to the test mode may be possible with said ROM being disconnected from said second bus line, when said security flag indicates the test mode after shipment.

6. A memory data protection circuit according to claim 5, wherein said security flag monitor circuit further outputs a signal for erasing the data in said nonvolatile memory, when said security flag indicates the test mode after shipment.