PCI bus with reduced number of signals

• US 5,826,048 A
• Filed: 01/31/1997
• Issued: 10/20/1998
• Est. Priority Date: 01/31/1997
• Status: Expired due to Term

• Current Assignee: ST Wireless SA, ST-Ericcson SA (Telefonaktiebolaget LM Ericsson)
• Original Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Inventors: Dempsey, Morgan James, Jayavant, Rajeev
• Primary Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US08/790,303
• Time in Patent Office: 627 Days
• Field of Search: 395/306, 395/308, 395/309, 395/285
• US Class Current: 710/306
• CPC Class Codes: G06F 13/4018 with data-width conversion

Abstract

A Mini-PCI (MPCI) interface, and associated circuits and methods are provided for connecting a Peripheral Component Interconnect (PCI) device to one or more external devices. The MPCI interface, circuits and methods provide for a substantial if not full implementation of a PCI Local Bus without requiring the standard number of pins, traces, or signals. The MPCI interface includes a PCI/MPCI bridge connected between a PCI bus and to up to eight external devices in the form of MPCI devices and linear memory devices. The PCI/MPCI bridge is capable of receiving an incoming PCI transaction and multiplexing some of its signals together to create a corresponding incoming MPCI transaction. This incoming MPCI transaction may then be passed over an MPCI bus, having fewer lines and optimally operating at a higher frequency, the external devices. The process is reversed for outgoing transactions, i.e., the MPCI transactions are de-multiplexed to create PCI transactions. Additionally, the MPCI interface may also be configured to provide for direct access to linearly addressed memory devices without adding a PCI interface to the external interface. The invention may be implemented through integrated circuitry and/or computer implemented instructions, and may be included within a personal computer.

Claims

1. An apparatus comprising:

a CPU;

a PCI bus coupled to said CPU;

a first PCI/MPCI bridge coupled to said PCI bus and configured to be accessed by said CPU via said PCI bus;

a MPCI bus coupled to said first PCI/MPCI bridge; and

an external device coupled to said MPCI bus and configured to be accessed by said first PCI/MPCI bridge via said MPCI bus,

wherein said first PCI/MPCI bridge is further configured to convert an incoming PCI transaction as received via said PCI bus into an incoming MPCI transaction by time-division multiplexing two or more incoming PCI signals within said incoming PCI transaction into a single incoming MPCI signal, and converting an outgoing MPCI transaction as received via said MPCI bus into an outgoing PCI transaction by de-multiplexing at least one outgoing MPCI signal within said outgoing MPCI transaction into two or more outgoing PCI signals, and wherein said incoming PCI transaction includes a plurality of incoming PCI signals and said outgoing PCI transaction includes a plurality of outgoing PCI signals which are selected from a group consisting of control signals, address signals and data signals.

2. The apparatus as recited in claim 1 wherein said first PCI/MPCI bridge further comprises:

a PCI-to-PCI bridge circuit coupled to said PCI bus and configured to receive said incoming PCI transaction via said PCI bus; and

a multiplexing/de-multiplexing stage coupled to said PCI-to-PCI bridge circuit and said MPCI bus, wherein said multiplexing/de-multiplexing stage is configured to convert said incoming PCI transaction as received from said PCI-to-PCI bridge circuit into said incoming MPCI transaction by time-division multiplexing two or more of said plurality of incoming PCI signals into said single incoming MPCI signal in response to one or more of said plurality of incoming PCI signals.

3. The apparatus as recited in claim 2 wherein said multiplexing/demultiplexing stage comprises:

a plurality of incoming multiplexers coupled to said MPCI bus; and

an incoming register file coupled to said PCI-to-PCI bridge circuit and configured to receive and buffer one or more of said plurality of incoming PCI signals and to supply said buffered incoming PCI signals to said plurality of incoming multiplexers.

4. The apparatus as recited in claim 2 wherein:

said multiplexing/de-multiplexing stage is further configured to convert said outgoing MPCI transaction as received via said MPCI bus into said outgoing PCI transaction by time-division de-multiplexing at least one of said plurality of outgoing MPCI signals within said outgoing MPCI transaction into said two or more outgoing PCI signals in response to one or more of said plurality of outgoing MPCI signals; and

said PCI-to-PCI bridge circuit is further configured to receive said outgoing PCI transaction from said multiplexing/de-multiplexing stage and to output said outgoing PCI transaction on said PCI bus.

5. The apparatus as recited in claim 4 wherein said multiplexing/de-multiplexing stage further comprises:

a plurality of outgoing de-multiplexers coupled to said MPCI bus; and

an outgoing register file coupled to said plurality of outgoing de-multiplexers and configured to receive and buffer one or more of said plurality of outgoing PCI signals therefrom and to supply said buffered outgoing PCI signals to said PCI-to-PCI bridge circuit.

6. The apparatus as recited in claim 1 wherein said external device is a MPCI device that is configured to receive said incoming MPCI transactions from said first PCI/MPCI bridge via said MPCI bus, and supply said outgoing MPCI transactions to said first PCI/MPCI bridge via said MPCI bus.

7. The apparatus as recited in claim 1 wherein said external device comprises:

a PCI device; and

a second PCI/MPCI bridge coupled to said PCI device and said MPCI bus and configured to convert said incoming MPCI transaction received via said MPCI bus into said incoming PCI transaction which is then supplied to said PCI device, and convert said outgoing PCI transaction received from said PCI device into said outgoing MPCI transaction which is then output onto said MPCI bus.

8. The apparatus as recited in claim 1 wherein said external device is a linearly addressed device coupled directly to said MPCI bus, and wherein said PCI/MPCI bridge provides selective access to said linearly addressed memory device in response to said incoming PCI transaction based on one or more incoming PCI signals.

9. The apparatus as recited in claim 8 wherein said linearly addressed device is accessed via said incoming an outgoing MPCI transactions over said MPCI bus.

10. The apparatus as recited in claim 8 wherein said linearly addressed device is accessed via said incoming and outgoing MPCI transactions over said MPCI bus and via an external data bus.

11. The apparatus as recited in claim 1 further comprising:

a host bus coupled to said CPU; and

a chip set coupled between said host bus and said PCI bus, wherein said host bus and said chip set are operatively configured to couple said CPU to said PCI bus.

12. A circuit for coupling one or more external devices to a PCI bus, said circuit comprising:

a PCI-to-PCI bridge capable of being coupled to said PCI bus and configured to send and receive PCI transactions over said PCI bus, wherein each of said PCI transactions includes a plurality of PCI signals which are selected from a group consisting of control signals, address signals and data signals; and

a multiplexing/de-multiplexing stage coupled to said PCI-to-PCI bridge and configured to convert at least one of said PCI transactions into at least one MPCI transaction comprising a plurality of MPCI signals, by time-division multiplexing two or more of said plurality of PCI signals into at least one of said plurality of MPCI signals, and to convert said MPCI transactions into at least one PCI transaction, by time-division de-multiplexing one or more of said plurality of MPCI signals to create at least two of said plurality of PCI signals, and wherein said multiplexing/de-multiplexing stage is capable of being coupled to said at least one of said one or more external devices so as to receive MPCI transactions therefrom and send MPCI transactions thereto.

13. The circuit as recited in claim 12 wherein said multiplexing/de-multiplexing stage further comprises a register file coupled to said PCI-to-PCI bridge and operatively configured to temporarily store therein one or more of said plurality of PCI signals as received from said PCI-to-PCI bridge.

14. The circuit as recited in claim 12 wherein said multiplexing/de-multiplexing stage further comprises a register file capable of being coupled to at least one of said one or more external devices and operatively configured to temporarily store one or more of said plurality of PCI signals following conversion from said MPCI transaction to said PCI transaction.

15. The circuit as recited in claim 12 wherein said multiplexing is controlled via one or more of said plurality of said PCI signals, and said de-multiplexing is controlled via one or more of said plurality of said MPCI signals.

16. A method for coupling a PCI bus to one or more external devices, said method comprising:

receiving an incoming PCI transaction from said PCI bus, wherein said incoming PCI transaction includes a plurality of incoming PCI signals selected from a group consisting of control signals, address signals and data signals;

time-division multiplexing at least two of said plurality of incoming PCI signals to generate at least one incoming MPCI signal;

time-division de-multiplexing said incoming MPCI signal to re-generate said at least two of said plurality of incoming PCI signals; and

providing said re-generated plurality of incoming PCI signals to said one or more external devices.

17. The method as recited in claim 16 further comprising:

receiving an outgoing PCI transaction from said one or more external devices, wherein said outgoing PCI transaction includes a plurality of outgoing PCI signals selected from a group consisting of control signals, address signals and data signals;

time-division multiplexing at least two of said plurality of outgoing PCI signals to generate at least one outgoing multiplexed MPCI signal;

time-division de-multiplexing said outgoing multiplexed MPCI signal to re-generate said at least two of said plurality of outgoing PCI signals; and

providing said re-generated plurality of outgoing PCI signals to said PCI bus.

18. The method as recited in claim 17 wherein said multiplexing is controlled via one or more of said plurality of said outgoing PCI signals, and said de-multiplexing is controlled via one or more non-multiplexed outgoing MPCI signals.

19. The method as recited in claim 17 further comprising temporarily storing one or more of said plurality of said outgoing PCI signals prior to said time-division multiplexing.

20. The method as recited in claim 16 wherein said multiplexing is controlled via one or more of said plurality of said incoming PCI signals, and said de-multiplexing is controlled via one or more non-multiplexed incoming MPCI signals.

21. The method as recited in claim 16 further comprising temporarily storing one or more of said plurality of incoming PCI signals prior to said time-division multiplexing.

22. A means for coupling one or more external devices to a PCI bus, said means comprising:

a bridge means for sending and receiving PCI transactions over said PCI bus; and

a conversion means for converting at least one of said PCI transactions into at least one second bus transaction comprising a plurality of second bus signals, by time-division multiplexing two or more of a plurality of PCI signals within said PCI transaction into at least one of said plurality of second bus signals, and converting said second bus transactions into at least one PCI transaction, by time-division de-multiplexing one or more of said plurality of second bus signals to create at least two of said plurality of PCI signals.