System and method for retiring instructions in a superscalar microprocessor

• US 5,826,055 A
• Filed: 06/07/1995
• Issued: 10/20/1998
• Est. Priority Date: 07/08/1991
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Wang, Johannes, Garg, Sanjiv, Deosaran, Trevor
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): VU, VIET DUY
• Application Number:
  US08/481,146
• Time in Patent Office: 1,231 Days
• Field of Search: 395/375, 395/800, 395/393, 395/394, 395/395
• US Class Current: 712/218
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/384 Register renaming
• CPC Class Codes: G06F 9/3853 of compound instructions
• CPC Class Codes: G06F 9/3856 Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory

Abstract

An system and method for retiring instructions in a superscalar microprocessor which executes a program comprising a set of instructions having a predetermined program order, the retirement system for simultaneously retiring groups of instructions executed in or out of order by the microprocessor. The retirement system comprises a done block for monitoring the status of the instructions to determine which instruction or group of instructions have been executed, a retirement control block for determining whether each executed instruction is retirable, a temporary buffer for storing results of instructions executed out of program order, and a register array for storing retirable-instruction results. In addition, the retirement control block further controls the retiring of a group of instructions determined to be retirable, by simultaneously transferring their results from the temporary buffer to the register array, and retires instructions executed in order by storing their results directly in the register array. The method comprises the steps of monitoring the status of the instructions to determine which group of instructions have been executed, determining whether each executed instruction is retirable, storing results of instructions executed out of program order in a temporary buffer, storing retirable-instruction results in a register array and retiring a group of retirable instructions by simultaneously transferring their results from the temporary buffer to the register array, and retiring instructions executed in order by storing their results directly in the register array.

Claims

1. A superscalar processor that executes a group of instructions out of a program order, the superscalar processor comprising:

means for assigning tags to instructions;

an index-addressable temporary buffer for storing results of executed instructions, wherein at least part of a tag assigned to an instruction indicates a location in said index-addressable temporary buffer where an execution result for the instruction is to be stored;

a register array for storing results of instructions that are retirable;

means for determining whether an executed instruction is retirable, wherein an executed instruction is retirable if there are no unexecuted instructions appearing earlier in program order relative to said executed instruction; and

means, coupled to said temporary buffer and said register array, for retiring approximately simultaneously a group of retirable instructions by transferring execution results of said group of retirable instructions from said index-addressable temporary buffer to said register array, wherein said execution results of said group of retirable instructions are retrieved from said index-addressable temporary buffer based on at least part of each tag assigned to an instruction in said group of retirable instructions.

2. The superscalar processor of claim 1, wherein the value of a tag is based on the location of said instruction in an instruction window.

3. The superscalar processor of claim 1, further comprising means for retiring instructions executed in said program order by transferring an execution result directly from a functional unit to said register array.

4. The superscalar processor of claim 1, wherein said group of retirable instructions includes at least two instructions.

5. The superscalar processor of claim 1, wherein said group of retirable instructions includes four instructions.

6. The superscalar processor of claim 1, wherein said means for retiring simultaneously transfers more than one instruction execution result from said temporary buffer to said register array.

7. The superscalar processor of claim 1, further comprising:

means for assigning done flags to one or more instructions determined to have been executed, and

wherein said means for determining includes means for checking said done flags to determine whether all instructions appearing earlier in the program order have completed to thereby determine whether each executed instruction is retirable.

8. The superscalar processor of claim 1, further comprising:

selection logic means that receives execution results of one or more retirable instructions from said index-addressable temporary buffer, directly receives execution results of instructions that have been executed by a functional unit, and selectively transfers execution results to said register array.

9. The superscalar processor of claim 1, wherein said index-addressable temporary buffer comprises:

a plurality of storage locations for storing the results of instructions executed out of program order according to said tags generated by said tag assignment means;

a plurality of address ports coupled to said plurality of storage locations, for receiving at least part of said tags to thereby address said plurality of storage locations to store the results;

a plurality of input ports coupled to said plurality of storage locations, for receiving the results to be stored in said index-addressable temporary buffer;

a first plurality of output ports coupled to said plurality of storage locations for outputting the results to said register array; and

a second plurality of output ports coupled to said plurality of storage locations for outputting the results to one or more functional units in the superscalar processor.

10. The superscalar processor of claim 1, wherein said means for retiring simultaneously transfers execution results of more than one instruction from said index-addressable temporary buffer to said register array in a single clock cycle.

11. A method for retiring instructions in a processor which executes a group of instructions out of a program order, comprising the steps of:

(1) assigning tags to instructions;

(2) determining whether an executed instruction is retirable, wherein an executed instruction is retirable if there are no unexecuted instructions appearing earlier in program order relative to said executed instruction;

(3) storing results of executed instructions in an index-addressable temporary buffer addressed by said tags, wherein at least part of a tag assigned to an instruction indicates a location in said index-addressable temporary buffer where an execution result for the instruction is to be stored; and

(4) retiring approximately simultaneously a group of retirable instructions, wherein said step of retiring comprises the step of transferring execution results of said group of retirable instructions from said index-addressable temporary buffer to a register array, wherein said execution results of said group of retirable instructions are retrieved from said index-addressable temporary buffer based on at least part of each tag assigned to an instruction in said group of retirable instructions.

12. The method of claim 11, wherein said step (1) comprises the step of assigning a tag to an instruction, wherein the value of a tag is based on the location of said instruction in an instruction window.

13. The method of claim 11, further comprising the step of:

(5) retiring instructions executed in program order by transferring an execution result directly from a functional unit to said register array.

14. The method of claim 11, wherein said step (4) comprises the step of retiring a group of instructions that includes at least two instructions.

15. The method of claim 11, wherein said step (4) comprises the step of retiring a group of instructions that includes four instructions.

16. The method of claim 11, wherein said step (4) comprises the step of simultaneously transferring execution results of more than one instruction from said index-addressable temporary buffer to said register array.

17. The method of claim 11, wherein said step (3) comprises the steps of:

assigning done flags to the instruction or instructions determined to have been executed; and

checking said done flags to determine whether all instructions appearing earlier in the program order have completed to thereby determine whether each executed instruction is retirable.

18. The method of claim 11, wherein said step (4) comprises the step of simultaneously transferring execution results of more than one instruction from said index-addressable temporary buffer to said register array in a single clock cycle.

19. A superscalar processor that executes a group of instructions out of a program order, the superscalar processor comprising:

means for determining whether an executed instruction is retirable, wherein an executed instruction is considered retirable if there are no unexecuted instructions appearing earlier in a program order;

a temporary buffer for storing results of instructions that are executed, at least one of said instructions being executed out of a program order;

a register array that stores execution results of retirable instructions, said register array receiving execution results that are transferred from said temporary buffer, said register array further receiving execution results that are transferred directly from a functional unit.

20. The superscalar processor of claim 19, wherein said temporary buffer is an index-addressable temporary buffer, execution results in said index-addressable temporary buffer being addressable by tags that include an address of a storage location in said index-addressable temporary buffer.

21. The superscalar processor of claim 20, further comprising tag assignment means for generating one or more tags to specify the storage location of execution results in said index-addressable temporary buffer, wherein the value of a tag for an instruction is based on the location of said instruction in an instruction window.

22. The superscalar processor of claim 19, wherein execution results of more than one instruction is transferred approximately simultaneously from said temporary buffer to said register array.

23. The superscalar processor of claim 19, wherein execution results of at least two instructions are transferred from said temporary buffer to said register array in a single clock cycle.

24. The superscalar processor of claim 19, wherein execution results of four instructions are transferred from said temporary buffer to said register array in a single clock cycle.

25. The superscalar processor of claim 19, further comprising:

means for assigning done flags to one or more instructions determined to have been executed, and

wherein said means for determining includes means for checking said done flags to determine whether all instructions appearing earlier in the program order have completed to thereby determine whether each executed instruction is retirable.

26. The superscalar processor of claim 19, further comprising:

selection logic means that receives execution results of one or more retirable instructions from said temporary buffer, directly receives execution results of instructions that have been executed by a functional unit, and selectively transfers execution results to said register array.

27. The superscalar processor of claim 19, wherein said temporary buffer comprises:

a plurality of storage locations for storing the results of instructions executed out of program order according to said tags generated by said tag assignment means;

a plurality of address ports coupled to said plurality of storage locations, for receiving at least part of said tags to thereby address said plurality of storage locations to store the results;

a plurality of input ports coupled to said plurality of storage locations, for receiving the results to be stored in said temporary buffer;

a first plurality of output ports coupled to said plurality of storage locations for outputting the results to said register array; and

a second plurality of output ports coupled to said plurality of storage locations for outputting the results to one or more functional units in the superscalar processor.

28. A method for retiring instructions in a processor which executes a group of instructions out of a program order, comprising the steps of:

(1) determining whether an executed instruction is retirable, wherein an executed instruction is retirable if there are no unexecuted instructions appearing earlier in a program order;

(2) storing results of executed instructions in a temporary buffer, wherein at least one of said instructions is executed out of a program order;

(3) transferring execution results of at least one instruction from said temporary buffer to a register array; and

(4) transferring at least one execution result directly from a functional unit to said register array.

29. The method of claim 28, wherein said step (2) comprises the step of storing results of executed instructions in an index-addressable temporary buffer, wherein execution results in said index-addressable temporary buffer are addressable by tags that include an address of a storage location in said index-addressable temporary buffer.

30. The method of claim 29, further comprising the step of generating one or more tags to specify the storage location of execution results in said index-addressable temporary buffer, wherein the value of a tag for an instruction is based on the location of said instruction in an instruction window.

31. The method of claim 28, wherein said step (3) comprises the step of transferring execution results of more than one instruction approximately simultaneously from said temporary buffer to said register array.

32. The method of claim 28, wherein said step (3) comprises the step of transferring execution results of at least two instructions from said temporary buffer to said register array in a single clock cycle.

33. The method of claim 28, wherein said step (3) comprises the step of transferring execution results of four instructions from said temporary buffer to said register array in a single clock cycle.

34. The method of claim 28, further comprising the steps of:

assigning done flags to one or more instructions determined to have been executed, and

checking said done flags to determine whether all instructions appearing earlier in the program order have completed to thereby determine whether each executed instruction is retirable.

35. A computer system, comprising:

a memory unit for storing program instructions;

a bus coupled to said memory unit for retrieving said program instructions; and

a processor coupled to said bus, wherein said processor comprises an instruction retirement system, including

means for determining whether an executed instruction is retirable, wherein an executed instruction is retirable if there are no unexecuted instructions appearing earlier in a program order;

a temporary buffer for storing results of executed instructions, wherein at least one of said instructions being executed out of a program order;

a register array that stores execution results of retirable instructions, said register array receiving execution results from said temporary buffer, said register array further receiving execution results directly from a functional unit.

36. The computer system of claim 35, wherein said temporary buffer is an indexaddressable temporary buffer, execution results in said index-addressable temporary buffer being addressable by tags that include an address of a storage location in said index-addressable temporary buffer.

37. The computer system of claim 36, further comprising tag assignment means for generating one or more tags to specify the storage location of execution results in said index-addressable temporary buffer, wherein the value of a tag for an instruction is based on the location of said instruction in an instruction window.

38. The computer system of claim 35, wherein execution results of more than one instruction are transferred approximately simultaneously from said temporary buffer to said register array.

39. The computer system of claim 35, wherein execution results from at least two instructions are transferred from said temporary buffer to said register array in a single clock cycle.

40. The computer system of claim 35, wherein execution results of four instructions are transferred from said temporary buffer to said register array in a single clock cycle.

41. The computer system of claim 35, further comprising:

means for assigning done flags to one or more instructions determined to have been executed, and

wherein said means for determining includes means for checking said done flags to determine whether all instructions appearing earlier in the program order have completed to thereby determine whether each executed instruction is retirable.

42. The computer system of claim 35, further comprising:

selection logic means that receives execution results of one or more retirable instructions from said temporary buffer, directly receives execution results of instructions that have been executed by a functional unit, and selectively transfers execution results to said register array.

43. The computer system of claim 35, wherein said temporary buffer comprises:

a plurality of storage locations for storing the results of instructions executed out of program order according to said tags generated by said tag assignment means;

a plurality of address ports coupled to said plurality of storage locations, for receiving at least part of said tags to thereby address said plurality of storage locations to store the execution results;

a plurality of input ports coupled to said plurality of storage locations, for receiving the execution results to be stored in said temporary buffer;

a first plurality of output ports coupled to said plurality of storage locations for outputting the execution results to said register array; and

a second plurality of output ports coupled to said plurality of storage locations for outputting the execution results to one or more functional units in the superscalar processor.

44. A computer system, comprising:

a memory unit for storing program instructions;

a bus coupled to said memory unit for retrieving said program instructions; and

a processor coupled to said bus, wherein said processor comprises an instruction retirement system, including

means for assigning tags to instructions;

an index-addressable temporary buffer for storing results of executed instructions, wherein at least part of a tag assigned to an instruction indicates a location in said index-addressable temporary buffer where an execution result for the instruction is to be stored;

a register array for storing execution results of instructions that are retirable;

means for determining whether an executed instruction is retirable, wherein an executed instruction is retirable if there are no unexecuted instructions appearing earlier in program order relative to said executed instruction; and

means, coupled to said temporary buffer and said register array, for retiring approximately simultaneously a group of retirable instructions by transferring execution results of said group of retirable instructions from said index-addressable temporary buffer to said register array, wherein said execution results of said group of retirable instructions are retrieved from said index addressable temporary buffer based on at least part of each tag assigned to an instruction in said group of retirable instructions.

45. The computer system of claim 44, wherein the value of a tag is based on the location of said instruction in an instruction window.

46. The computer system of claim 44, further comprising means for retiring instructions executed in said program order by transferring an execution result directly from a functional unit to said register array.

47. The computer system of claim 44, wherein said group of retirable instructions includes at least two instructions.

48. The computer system of claim 44, wherein said group of retirable instructions includes four instructions.

49. The computer system of claim 44, wherein said means for retiring simultaneously transfers more than one instruction execution result from said temporary buffer to said register array.

50. The computer system of claim 44, further comprising:

means for assigning done flags to one or more instructions determined to have been executed, wherein said means for determining includes means for checking said done flags to determine whether all instructions appearing earlier in the program order have completed to thereby determine whether each executed instruction is retirable.

51. The computer system of claim 44, further comprising:

selection logic means that receives execution results of one or more retirable instructions from said index-addressable temporary buffer, directly receives execution results of instructions that have been executed by a functional unit, and selectively transfers execution results to said register array.

52. The computer system of claim 44, wherein said index-addressable temporary buffer comprises:

a plurality of storage locations for storing the results of instructions executed out of program order according to said tags generated by said tag assignment means;

a plurality of address ports coupled to said plurality of storage locations, for receiving at least part of said tags to thereby address said plurality of storage locations to store the results;

a plurality of input ports coupled to said plurality of storage locations, for receiving the results to be stored in said index-addressable temporary buffer;

a first plurality of output ports coupled to said plurality of storage locations for outputting the results to said register array; and

a second plurality of output ports coupled to said plurality of storage locations for outputting the results to one or more functional units in the superscalar processor.