Integrated circuit with a serial port having only one pin

• US 5,826,068 A
• Filed: 06/07/1995
• Issued: 10/20/1998
• Est. Priority Date: 11/09/1994
• Status: Expired due to Term

• Current Assignee: PMC-Sierra Incorporated (Microchip Technology Incorporated)
• Original Assignee: Adaptec Incorporated (Steel Partners Holdings LP)
• Inventors: Gates, Stillman F.
• Primary Examiner(s): An, Meng-Ai T.
• Assistant Examiner(s): FOLLANSBEE, JOHN A
• Application Number:
  US08/482,529
• Time in Patent Office: 1,231 Days
• Field of Search: 395/200.21, 395/200.02, 395/200.01, 395/820, 395/681, 395/286, 395/304, 395/873, 395/881, 395/556, 395/559, 370/278
• US Class Current: 713/600
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4295 using an embedded synchronisation

Abstract

A host adapter integrated circuit that contains data transfer modules has a serial port that uses a single serial port pin to communicate with a slave serial port input-output integrated circuit that interfaces to various resources that are included in a support circuit. The serial port forms a packet from each byte of information to be transferred from a module to the slave device by adding a start bit before the byte, followed by a parity bit at the end of the byte and followed by a stop bit. After transmitting the packet, the serial port waits for an acknowledge packet from the slave serial port input-output integrated circuit, for example for two clock cycles after transmission of the packet. For synchronous operation, a common oscillator drives the clock signal on the slave serial port input-output integrated circuit and host adapter integrated circuit. The serial port pin in the host adapter integrated circuit is connected to a shifter circuit in the serial port that serially clocks data from the serial port pin and passes the data parallelly to a bus in the host adapter integrated circuit and vice versa.

Claims

1. An integrated circuit comprising;

a clock terminal;

a first module coupled to said clock terminal wherein said first module receives a clock signal from said clock terminal and generates a buffered clock signal, said buffered clock signal and said clock signal having a common frequency;

a second module having a clock input line coupled to said first module wherein said buffered clock signal is supplied to said clock input line of said second module; and

a serial port having a clock input line coupled to said first module wherein said buffered clock signal is supplied to said clock input line of said serial port and further wherein said serial port further comprises;

a plurality of storage elements wherein each storage element is serially coupled to another storage element in said plurality of storage elements; and

a bidirectional pin coupled to at least one storage element in said plurality of storage elements wherein said bidirectional pin is the only pin in said serial port, and said bidirectional pin is used to transfer information serially from and to said integrated circuit;

wherein said serial port waits for a predetermined time period after transmission of a signal on said bidirectional pin to become sensitive to a signal received on said bidirectional pin.

2. An integrated circuit as in claim 1, wherein said plurality of storage elements comprise a plurality of flip-flops, and further wherein said serial port alternately stores in said plurality of storage elements an input signal received from said bidirectional pin and an output signal to be transmitted on said bidirectional pin.

3. An integrated circuit, as in claim 2, further comprising a plurality of multiplexers, wherein at least one of said multiplexers couples an output terminal of a first flip-flop to an input terminal of a second flip-flop, and further wherein said flip-flops are identical to each other and are clocked by said buffered clock signal.

4. An integrated circuit as in claim 1 further comprising:

a processor data bus; and

a processor address bus;

wherein said plurality of storage elements are coupled to said processor data bus and said processor address bus so that a processor coupled to said processor data bus and to said processor address bus can load data into said plurality of storage elements.

5. An integrated circuit as in claim 1 further comprising a shifter state machine wherein said bidirectional pin is coupled to said shifter state machine.

6. The integrated circuit of claim 1 wherein said serial port further comprises:

a line controller circuit coupled to said bidirectional pin;

wherein said line controller circuit transfers a first packet serially to said bidirectional pin; and

further wherein said line controller circuit receives a second packet serially from said bidirectional pin, said second packet being an acknowledge packet for receipt of said first packet.

7. The integrated circuit of claim 6,

wherein said line controller circuit further comprises a drive line, and said line controller circuit transfers said first packet to said bidirectional pin in response to an active signal on said drive line;

and

further wherein said line controller circuit receives said acknowledgment packet from said bidirectional pin only in response to an inactive signal on said drive line.

8. The integrated circuit of claim 6 wherein said line controller circuit comprises (i) an input buffer coupled to said bidirectional pin and (ii) an output driver coupled to said bidirectional pin and to said drive line;

wherein an active signal on said drive line enables said output driver to pass said command packet to said bidirectional pin; and

further wherein an inactive signal on said drive line disables said output driver to allow said input buffer to receive said acknowledgment packet from said bidirectional pin.

9. The integrated circuit of claim 8 wherein said output driver in said line controller circuit comprises at least one logic element, said logic element allowing passage of said command packet to said bidirectional pin in dependence on said signal on said drive line.

10. The integrated circuit of claim 6, wherein said serial port further comprises:

a state machine coupled to said line controller circuit, wherein;

said state machine drives a first signal active to said line controller circuit to indicate a need to transfer said command packet; and

said state machine drives a second signal active to said line controller circuit to indicate a need to receive said acknowledge packet.

13. The integrated circuit of claim 1, wherein said serial port transmits information on said bidirectional pin synchronous with said buffered clock signal.

14. The integrated circuit of claim 1 wherein the duration of said predetermined time period is at least two cycles in said clock signal.

15. The integrated circuit of claim 1 wherein said serial port waits for completion of the signal being received on said bidirectional pin before transmitting another signal on said bidirectional pin.

11. The integrated circuit of 10, wherein each of said command packet and said acknowledge packet has a start bit at the beginning and a stop bit at the end, said start bit having a first value and said stop bit having a second value different from said first value.

12. The integrated circuit of claim 11 wherein said bidirectional pin is pulled up to a default value equal to said second value.

16. An integrated circuit comprising:

a clock terminal;

a first module coupled to said clock terminal wherein said first module receives a clock signal from said clock terminal and generates a buffered clock signal, said buffered clock signal and said clock signal having a common frequency;

a second module having a clock input line coupled to said first module wherein said buffered clock signal is supplied to said clock input line of said second module; and

a serial port having a clock input line coupled to said first module wherein said buffered clock signal is supplied to said clock input line of said serial port and further wherein said serial port further comprises;

a plurality of storage elements wherein each storage element is serially coupled to another storage element in said plurality of storage elements; and

a bidirectional pin coupled to at least one storage element in said plurality of storage elements wherein said bidirectional pin is the only pin in said serial port, and said bidirectional pin is used to transfer information serially from and to said integrated circuit;

wherein said serial port waits for a predetermined time period after receipt of a signal on said bidirectional pin before transmission of a signal on said bidirectional pin.

17. The integrated circuit of claim 16, wherein said plurality of storage elements comprise a plurality of flip-flops, and further wherein said serial port alternately stores in said plurality of storage elements an input signal received from said bidirectional pin and an output signal to be transmitted on said bidirectional pin.

18. The integrated circuit of claim 17, further comprising a plurality of multiplexers, wherein at least one of said multiplexers couples an output terminal of a first flip-flop to an input terminal of a second flip-flop.

19. The integrated circuit of claim 16 further comprising:

a processor data bus; and

a processor address bus;

wherein said plurality of storage elements are coupled to said processor data bus and said processor address bus so that a processor coupled to said processor data bus and to said processor address bus can load data into said plurality of storage elements.

20. The integrated circuit of claim 19 further comprising a shifter state machine wherein said bidirectional pin is coupled to said shifter state machine.

21. The integrated circuit of claim 16, wherein said serial port transmits data on said bidirectional pin synchronous with said buffered clock signal.

22. The integrated circuit of claim 16 wherein said serial port further comprises:

a line controller circuit coupled to said bidirectional pin;

wherein said line controller circuit transmits a first packet serially on said bidirectional pin and said line controller circuit receives a second packet serially from said bidirectional pin, said second packet being an acknowledge packet for receipt of said first packet.

23. The integrated circuit of claim 22,

wherein said line controller circuit further comprises a drive line, and said line controller circuit transfers said first packet to said bidirectional pin in response to an active signal on said drive line;

and

further wherein said line controller circuit receives said acknowledgment packet from said bidirectional pin only in response to an inactive signal on said drive line.

24. The integrated circuit of claim 22 wherein said line controller circuit comprises (i) an input buffer coupled to said bidirectional pin and (ii) an output driver coupled to said bidirectional pin and to said drive line;

wherein an active signal on said drive line enables said output driver to pass said command packet to said bidirectional pin; and

further wherein an inactive signal on said drive line disables said output driver to allow said input buffer to receive said acknowledgment packet from said bidirectional pin.

25. The integrated circuit of claim 24 wherein said output driver in said line controller circuit comprises at least one logic element, said logic element allowing passage of said command packet to said bidirectional pin in dependence on said signal on said drive line.

26. The integrated circuit of claim 22, wherein said serial port further comprises:

a state machine coupled to said line controller circuit, wherein;

said state machine drives a first signal active to said line controller circuit to indicate a need to transfer said first packet; and

said state machine drives a second signal active to said line controller circuit to indicate a need to receive said second packet.

29. The integrated circuit of claim 16 wherein the duration of said predetermined time period is at least two cycles in said clock signal.

30. The integrated circuit of claim 16 wherein said serial port waits for completion of the signal being received on said bidirectional pin before transmitting another signal on said bidirectional pin.

27. The integrated circuit of 26, wherein each of said first packet and said second packet has a start bit at the beginning and a stop bit at the end, said start bit having a first value and said stop bit having a second value different from said first value.

28. The integrated circuit of claim 27 wherein said bidirectional pin is pulled to a default value equal to said second value.