Apparatus for dynamic XY tiled texture caching
First Claim
1. A graphics subsystem for rendering texture information representative of graphics primitive on a computer display, comprising:
- a host processor for generating display list information of parameter values defining said primitives;
a system memory coupled to said host processor for storing said display list information;
a graphics processor coupled to said host processor and said system memory for processing said texture map information;
wherein said graphics processor includes;
a register file for storing said display list of parameter values;
a polygon engine coupled to said register file for generating polygons responsive to said primitives; and
a texture control unit coupled to said register file for receiving said texture information and generating texture maps representative of said graphics primitives, comprising;
a texture engine for receiving the initial and incremental values of a texture to be fetched from said system memory, said texture engine further receiving polygon size information from said register file in order to track the exact number of texels to complete a primitive to be rendered; and
a static random access memory device disposed within said texture control unit for storing texture maps used to fill in polygons drawn by said polygon engine.
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Accused Products
Abstract
A graphics subsystem includes hardware for permitting tile texture data to be dynamically cached internally within the hardware. In addition, the system generates a SHIFT signal to permit automatic adjustment of tile texture parameters to facilitate retrieval of the cached texture maps. The system includes a 1 kbyte static random access memory internally disposed within a graphics processor to facilitate UV caching of the texture maps by the graphics processor. A cache controller also disposed within the graphics processor facilitates tile requests by other resources in the graphics subsystem to the internal static random access memory. The cache controller performs UV tile read hit comparisons and subsequent UV to linear address conversions to read texels from the internal static random access memory.
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Citations
21 Claims
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1. A graphics subsystem for rendering texture information representative of graphics primitive on a computer display, comprising:
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a host processor for generating display list information of parameter values defining said primitives; a system memory coupled to said host processor for storing said display list information; a graphics processor coupled to said host processor and said system memory for processing said texture map information; wherein said graphics processor includes; a register file for storing said display list of parameter values; a polygon engine coupled to said register file for generating polygons responsive to said primitives; and a texture control unit coupled to said register file for receiving said texture information and generating texture maps representative of said graphics primitives, comprising; a texture engine for receiving the initial and incremental values of a texture to be fetched from said system memory, said texture engine further receiving polygon size information from said register file in order to track the exact number of texels to complete a primitive to be rendered; and a static random access memory device disposed within said texture control unit for storing texture maps used to fill in polygons drawn by said polygon engine. - View Dependent Claims (2, 3)
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4. In a computer system having a graphics processor for processing graphics information, said graphics processor comprising:
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a register file internally disposed within said graphics processor to receive display list information defining graphics primitives to be rendered in said graphics processor; a polygon engine coupled to said register file to receive the initial and incremental values required to fully specify said primitive to be rendered; a texture engine coupled to said polygon engine to receive the initial and incremental values required to specify a texture map; and an internal memory device disposed within said graphics processor and coupled to said texture engine to internally store blocks of said texture map within said graphics processor in a tiled linear format. - View Dependent Claims (5, 6, 7)
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8. A graphics processor for processing graphics information, said graphics processor comprising:
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a texture control unit for processing texture information of graphics primitive corresponding to said graphics information; wherein said texture control unit comprises a texture engine coupled to a register file for receiving initial and incremental values of texture parameters corresponding to graphics primitives to be displayed; said texture engine comprising a polygon tracker interpolator coupled to said register file to receive polygon size information and to track the exact number of pixels per span on a display device; and an internal cache for temporarily storing said initial and incremental values of said texture parameters. - View Dependent Claims (9, 10, 11, 12)
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13. A texture cache controller disposed within a graphics processor for controlling texture information fetches from an internal storage device also disposed within said graphics processor;
- said texture cache controller comprising;
a cache tile hit detection logic unit for receiving UV address requests and determining whether a requested address currently exists in said internal memory device; a UV to linear address translator coupled to said cache tile hit logic detection unit to receive the UV address requests presented to said texture cache controller and to translate said UV addresses into linear address to be fetched from said internal storage device; and a UV tile fetch logic unit coupled to said UV to linear address translation unit to receive requested UV address locations from said UV to linear address translator. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21)
- said texture cache controller comprising;
Specification