Apparatus for dynamic XY tiled texture caching

• US 5,828,382 A
• Filed: 08/02/1996
• Issued: 10/27/1998
• Est. Priority Date: 08/02/1996
• Status: Expired due to Term

• Current Assignee: NVIDIA Corporation
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Wilde, Daniel P.
• Primary Examiner(s): Tung, Kee M.
• Application Number:
  US08/691,762
• Time in Patent Office: 816 Days
• Field of Search: 345/419, 345/425-431, 345/501, 345/507-509, 345/522, 711/118, 711/119, 711/121, 711/136, 711/202
• US Class Current: 345/552
• CPC Class Codes: G06T 15/04 Texture mapping

Abstract

A graphics subsystem includes hardware for permitting tile texture data to be dynamically cached internally within the hardware. In addition, the system generates a SHIFT signal to permit automatic adjustment of tile texture parameters to facilitate retrieval of the cached texture maps. The system includes a 1 kbyte static random access memory internally disposed within a graphics processor to facilitate UV caching of the texture maps by the graphics processor. A cache controller also disposed within the graphics processor facilitates tile requests by other resources in the graphics subsystem to the internal static random access memory. The cache controller performs UV tile read hit comparisons and subsequent UV to linear address conversions to read texels from the internal static random access memory.

Claims

1. A graphics subsystem for rendering texture information representative of graphics primitive on a computer display, comprising:

a host processor for generating display list information of parameter values defining said primitives;

a system memory coupled to said host processor for storing said display list information;

a graphics processor coupled to said host processor and said system memory for processing said texture map information;

wherein said graphics processor includes;

a register file for storing said display list of parameter values;

a polygon engine coupled to said register file for generating polygons responsive to said primitives; and

a texture control unit coupled to said register file for receiving said texture information and generating texture maps representative of said graphics primitives, comprising;

a texture engine for receiving the initial and incremental values of a texture to be fetched from said system memory, said texture engine further receiving polygon size information from said register file in order to track the exact number of texels to complete a primitive to be rendered; and

a static random access memory device disposed within said texture control unit for storing texture maps used to fill in polygons drawn by said polygon engine.

2. The graphics subsystem of claim 1 wherein said SRAM device is tiled internal to said graphics processor to store said texture maps.

3. The graphics subsystem of claim 2 wherein said SRAM device is divided into a number of cache tiles (ways) to hold UV sections of said texture maps.

4. In a computer system having a graphics processor for processing graphics information, said graphics processor comprising:

a register file internally disposed within said graphics processor to receive display list information defining graphics primitives to be rendered in said graphics processor;

a polygon engine coupled to said register file to receive the initial and incremental values required to fully specify said primitive to be rendered;

a texture engine coupled to said polygon engine to receive the initial and incremental values required to specify a texture map; and

an internal memory device disposed within said graphics processor and coupled to said texture engine to internally store blocks of said texture map within said graphics processor in a tiled linear format.

5. The computer system of claim 4 wherein said graphics processor further includes a three dimensional pixel pipe coupled to said texture engine and said polygon engine to receive polygon and texture data respectively and wherein said polygon and texture data are aligned as said polygon and texture data are loaded into said 3D pixel pipe in order to put the correct texel color into the correct pixel location.

6. The computer system of claim 4 wherein said internal memory device is a static random access memory (SRAM) device and wherein said SRAM device stores 64 byte blocks of a UV section of said texture information.

7. The computer system of claim 6 wherein said UV section of texture information represent the XY region of a texture map in a texture memory.

8. A graphics processor for processing graphics information, said graphics processor comprising:

a texture control unit for processing texture information of graphics primitive corresponding to said graphics information;

wherein said texture control unit comprises a texture engine coupled to a register file for receiving initial and incremental values of texture parameters corresponding to graphics primitives to be displayed;

said texture engine comprising a polygon tracker interpolator coupled to said register file to receive polygon size information and to track the exact number of pixels per span on a display device; and

an internal cache for temporarily storing said initial and incremental values of said texture parameters.

9. The graphics processor of claim 8 wherein said texture engine further includes a texture engine state machine coupled to said polygon tracker for receiving polygon size information and track the exact number of pixels per span on said display device.

10. The graphics processor of claim 9 wherein said texture engine further comprises texel address generators coupled to said register file to receive the base and incremental UV values required to generate the UV addresses of every texel fetched from said internal memory device.

11. The graphics processor of claim 10 wherein said texture engine includes a texel UV address First-In First-Out (FIFO) unit coupled to said texel address generators to receive said UV addresses generated by said texel address generators, said texel UV address generates VALID and POP to indicate when a valid UV address location is present in said internal storage device.

12. The graphics processor of claim 11 wherein said texture engine further includes a texture cache controller coupled to said texel address FIFO to receive said VALID signals and to generate UV tile fetch requests to said internal storage device.

13. A texture cache controller disposed within a graphics processor for controlling texture information fetches from an internal storage device also disposed within said graphics processor;

said texture cache controller comprising;

a cache tile hit detection logic unit for receiving UV address requests and determining whether a requested address currently exists in said internal memory device;

a UV to linear address translator coupled to said cache tile hit logic detection unit to receive the UV address requests presented to said texture cache controller and to translate said UV addresses into linear address to be fetched from said internal storage device; and

a UV tile fetch logic unit coupled to said UV to linear address translation unit to receive requested UV address locations from said UV to linear address translator.

14. The texture cache controller of claim 13 wherein said UV tile fetch logic unit generates write signals to said internal memory device to write new UV addresses to be stored in said internal storage device.

15. The texture cache controller of claim 14 wherein said cache tile hit detection logic unit includes a plurality of MUXes for receiving U and V texel addresses to calculate the U and V start address of a tile respectively.

16. The texture cache controller of claim 15 wherein said cache tile hit detection logic unit further includes a plurality of way controllers coupled to said MUXes to receive the U and V tile addresses respectively and generating an address present signal to indicate the presence of a requested tile address in said internal memory device.

17. The texture cache controller of claim 16 wherein said cache tile hit detection logic unit further includes a plurality of AND logic gates coupled to said way controllers for generating HIT and MISS signals indicating whether said way controllers find a requested tile address in said internal memory device or not.

18. The texture cache controller of claim 17 wherein said cache tile hit logic detection unit further includes an address encoder coupled to said plurality of way controllers to receive the load addresses to said internal memory device, wherein said address encoder performs a 16 to 4 address encode to generate a read way signal to said internal memory device to read tile addresses.

19. The cache controller of claim 18 wherein said fetch logic circuit includes a plurality of mask registers for generating mask values representing the V portion of a UV tile to calculate the V start address value of a tile which contains a requested texel from said internal memory device.

20. The cache controller of claim 19 wherein said fetch logic circuit includes fetch logic state machine logic coupled to said UV address generator mask for initiating request signals to memory source external to said graphics processor to fetch new UV tile address values if a fetch request to said internal memory device misses.

21. The cache controller of claim 18 wherein said fetch logic circuit further includes a least recently used (LRU) logic circuit coupled to said tag registers for receiving incoming tile address and determining which of the tiles in said internal memory device should be modified.